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path: root/target/arm/translate.h
AgeCommit message (Expand)AuthorFilesLines
2022-07-11target/arm: Implement SME MOVARichard Henderson1-0/+5
2022-07-11target/arm: Mark ADR as non-streamingRichard Henderson1-0/+7
2022-07-11target/arm: Trap non-streaming usage when Streaming SVE is activeRichard Henderson1-0/+4
2022-06-27target/arm: Add SVL to TB flagsRichard Henderson1-0/+1
2022-06-27target/arm: Add PSTATE.{SM,ZA} to TB flagsRichard Henderson1-0/+4
2022-06-27target/arm: Add SMEEXC_EL to TB flagsRichard Henderson1-0/+1
2022-06-10target/arm: Remove default_exception_elRichard Henderson1-16/+0
2022-06-10target/arm: Move gen_exception to translate.cRichard Henderson1-8/+0
2022-06-10target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_ELRichard Henderson1-2/+0
2022-06-10target/arm: Create helper_exception_swstepRichard Henderson1-9/+3
2022-06-10target/arm: Introduce gen_exception_insnRichard Henderson1-0/+1
2022-06-10target/arm: Rename gen_exception_insn to gen_exception_insn_elRichard Henderson1-2/+2
2022-06-10target/arm: Rename helper_exception_with_syndromeRichard Henderson1-3/+3
2022-06-08target/arm: Rename TBFLAG_A64 ZCR_LEN to VLRichard Henderson1-1/+1
2022-05-30target/arm: Introduce TRANS, TRANS_FEATRichard Henderson1-0/+11
2022-04-22target/arm: Use tcg_constant_i32 in translate.hRichard Henderson1-10/+3
2022-04-22target/arm: Change DisasContext.thumb to boolRichard Henderson1-1/+1
2022-04-22target/arm: Change DisasContext.aarch64 to boolRichard Henderson1-1/+1
2021-09-21target/arm: Add TB flag for "MVE insns not predicated"Peter Maydell1-0/+2
2021-09-13target/arm: Take an exception if PSTATE.IL is setPeter Maydell1-0/+2
2021-09-01target/arm: Implement MVE VADD (floating-point)Peter Maydell1-0/+6
2021-07-02target/arm: Implement MVE shifts by registerPeter Maydell1-0/+1
2021-07-02target/arm: Implement MVE shifts by immediatePeter Maydell1-0/+1
2021-07-02target/arm: Implement MVE long shifts by registerPeter Maydell1-0/+1
2021-07-02target/arm: Implement MVE long shifts by immediatePeter Maydell1-0/+1
2021-07-02target/arm: Implement MVE vector shift right by immediate insnsPeter Maydell1-0/+20
2021-07-02target/arm: Use asimd_imm_const for A64 decodePeter Maydell1-1/+2
2021-07-02target/arm: Make asimd_imm_const() publicPeter Maydell1-0/+16
2021-06-21target/arm: Implement MVE VMLALDAVPeter Maydell1-0/+10
2021-06-16target/arm: Add handling for PSR.ECI/ICIPeter Maydell1-0/+9
2021-05-10target/arm: Move NeonGenThreeOpEnvFn typedef to translate.hPeter Maydell1-0/+2
2021-05-10target/arm: Share unallocated_encoding() and gen_exception_insn()Peter Maydell1-0/+3
2021-05-10target/arm: Move constant expanders to translate.hPeter Maydell1-0/+24
2021-04-30target/arm: Enforce alignment for VLDn (all lanes)Richard Henderson1-0/+1
2021-04-30target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endiannessRichard Henderson1-0/+24
2021-04-30target/arm: Add ALIGN_MEM to TBFLAG_ANYRichard Henderson1-0/+2
2021-04-30target/arm: Move mode specific TB flags to tb->cs_baseRichard Henderson1-1/+1
2021-04-30target/arm: Introduce CPUARMTBFlagsRichard Henderson1-0/+11
2020-08-28target/arm: Rearrange {sve,fp}_check_access assertRichard Henderson1-0/+1
2020-08-24target/arm: Implement FPST_STD_F16 fpstatusPeter Maydell1-1/+2
2020-08-24target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr()Peter Maydell1-0/+51
2020-06-26target/arm: Implement the LDGM, STGM, STZGM instructionsRichard Henderson1-0/+2
2020-06-26target/arm: Add MTE bits to tb_flagsRichard Henderson1-0/+5
2020-06-26target/arm: Add DISAS_UPDATE_NOCHAINRichard Henderson1-0/+2
2020-06-26target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXITRichard Henderson1-6/+8
2020-06-23target/arm: Convert simple fp Neon 2-reg-misc insnsPeter Maydell1-0/+1
2020-06-23target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetreePeter Maydell1-0/+1
2020-06-23target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefsPeter Maydell1-2/+2
2020-06-23target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFnPeter Maydell1-1/+1
2020-06-16target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetreePeter Maydell1-0/+1