riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-07-19	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	1	-3/+3
2017-07-19	target/arm: optimize aarch32 rev16	Aurelien Jarno	1	-2/+4
2017-07-17	target/arm: use DISAS_EXIT for eret handling	Alex Bennée	1	-2/+4
2017-07-17	target/arm: use gen_goto_tb for ISB handling	Alex Bennée	1	-2/+2
2017-07-17	target/arm/translate: ensure gen_goto_tb sets exit flags	Alex Bennée	1	-1/+5
2017-07-17	target/arm/translate: make DISAS_UPDATE match declared semantics	Alex Bennée	1	-3/+3
2017-06-05	target/arm: optimize indirect branches	Emilio G. Cota	1	-9/+16
2017-06-05	target/arm: optimize cross-page direct jumps in softmmu	Emilio G. Cota	1	-1/+5
2017-06-02	arm: Implement HFNMIENA support for M profile MPU	Peter Maydell	1	-0/+1
2017-06-02	arm: Use different ARMMMUIdx values for M profile	Peter Maydell	1	-0/+3
2017-06-02	arm: Add support for M profile CPUs having different MMU index semantics	Peter Maydell	1	-5/+5
2017-04-20	arm: Remove workarounds for old M-profile exception return implementation	Peter Maydell	1	-8/+0
2017-04-20	arm: Implement M profile exception return properly	Peter Maydell	1	-6/+60
2017-04-20	arm: Track M profile handler mode state in TB flags	Peter Maydell	1	-0/+1
2017-04-20	arm: Abstract out "are we singlestepping" test to utility function	Peter Maydell	1	-5/+15
2017-04-20	arm: Move condition-failed codepath generation out of if()	Peter Maydell	1	-13/+11
2017-04-20	arm: Move gen_set_condexec() and gen_set_pc_im() up in the file	Peter Maydell	1	-16/+15
2017-04-20	arm: Factor out "generate right kind of step exception"	Peter Maydell	1	-12/+16
2017-04-20	arm: Thumb shift operations should not permit interworking branches	Peter Maydell	1	-1/+1
2017-04-20	arm: Don't implement BXJ on M-profile CPUs	Peter Maydell	1	-1/+6
2017-03-20	arm: Fix APSR writes via M profile MSR	Peter Maydell	1	-1/+2
2017-03-20	arm: Enforce should-be-1 bits in MRS decoding	Peter Maydell	1	-0/+14
2017-03-20	arm: Don't decode MRS(banked) or MSR(banked) for M profile	Peter Maydell	1	-2/+4
2017-03-20	arm: HVC and SMC encodings don't exist for M profile	Peter Maydell	1	-0/+3
2017-02-28	armv7m: Raise correct kind of UsageFault for attempts to execute ARM code	Peter Maydell	1	-2/+6
2017-02-24	target-arm: don't generate WFE/YIELD calls for MTTCG	Alex Bennée	1	-4/+16
2017-02-07	target/arm: A32, T32: Create Instruction Syndromes for Data Aborts	Peter Maydell	1	-49/+135
2017-02-07	target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode	Peter Maydell	1	-3/+6
2017-01-27	armv7m: Report no-coprocessor faults correctly	Peter Maydell	1	-0/+8
2017-01-27	armv7m: Replace armv7m.hack with unassigned_access handler	Michael Davidsaver	1	-6/+6
2017-01-10	target-arm: Use clz opcode	Richard Henderson	1	-3/+3
2017-01-10	target-arm: Use new deposit and extract ops	Richard Henderson	1	-29/+8
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+12055