| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-02-28 | armv7m: Raise correct kind of UsageFault for attempts to execute ARM code | Peter Maydell | 1 | -2/+6 |
| 2017-02-24 | target-arm: don't generate WFE/YIELD calls for MTTCG | Alex Bennée | 1 | -4/+16 |
| 2017-02-07 | target/arm: A32, T32: Create Instruction Syndromes for Data Aborts | Peter Maydell | 1 | -49/+135 |
| 2017-02-07 | target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode | Peter Maydell | 1 | -3/+6 |
| 2017-01-27 | armv7m: Report no-coprocessor faults correctly | Peter Maydell | 1 | -0/+8 |
| 2017-01-27 | armv7m: Replace armv7m.hack with unassigned_access handler | Michael Davidsaver | 1 | -6/+6 |
| 2017-01-10 | target-arm: Use clz opcode | Richard Henderson | 1 | -3/+3 |
| 2017-01-10 | target-arm: Use new deposit and extract ops | Richard Henderson | 1 | -29/+8 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+12055 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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