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path: root/target/arm/translate.c
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2017-11-07translate.c: Fix usermode big-endian AArch32 LDREXD and STREXDPeter Maydell1-5/+34
2017-10-31fix WFI/WFE length in syndrome registerStefano Stabellini1-1/+9
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-2/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-2/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-4/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24target/arm: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-2/+7
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-12target/arm: Implement SG instruction corner casesPeter Maydell1-1/+22
2017-10-12target/arm: Support some Thumb insns being always unconditionalPeter Maydell1-1/+47
2017-10-12target-arm: Simplify insn_crosses_page()Peter Maydell1-21/+6
2017-10-12target/arm: Pull Thumb insn word loads up to top levelPeter Maydell1-70/+108
2017-10-12target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1Peter Maydell1-2/+1
2017-10-12target/arm: Implement secure function returnPeter Maydell1-2/+12
2017-10-12target/arm: Implement BLXNSPeter Maydell1-2/+15
2017-10-12target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()Peter Maydell1-0/+4
2017-10-10tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota1-4/+1
2017-09-07Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'...Peter Maydell1-4/+50
2017-09-07target/arm: Add Jazelle featurePortia Stephens1-1/+1
2017-09-07target/arm: Implement BXNS, and banked stack pointersPeter Maydell1-1/+41
2017-09-07target/arm: Make CONTROL register banked for v8MPeter Maydell1-1/+1
2017-09-07target/arm: Add state field, feature bit and migration for v8M secure statePeter Maydell1-1/+7
2017-09-06target/arm: Perform per-insn cross-page check only for ThumbRichard Henderson1-25/+33
2017-09-06target/arm: Split out thumb_tr_translate_insnRichard Henderson1-41/+80
2017-09-06target/arm: Move ss check to init_disas_contextRichard Henderson1-5/+8
2017-09-06target/arm: [tcg] Port to generic translation frameworkLluís Vilanova1-87/+22
2017-09-06target/arm: [tcg] Port to disas_logLluís Vilanova1-5/+13
2017-09-06target/arm: [tcg] Port to tb_stopLluís Vilanova1-77/+84
2017-09-06target/arm: [tcg] Port to translate_insnLluís Vilanova1-75/+90
2017-09-06target/arm: [tcg,a64] Port to insn_startLluís Vilanova1-20/+35
2017-09-06target/arm: [tcg] Port to insn_startLluís Vilanova1-4/+11
2017-09-06target/arm: [tcg] Port to tb_startLluís Vilanova1-38/+44
2017-09-06target/arm: [tcg] Port to init_disas_contextLluís Vilanova1-38/+50
2017-09-06target/arm: [tcg] Port to DisasContextBaseLluís Vilanova1-59/+58
2017-09-06target/arm: Delay check for magic kernel pageRichard Henderson1-11/+11
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-1/+1
2017-09-06target/arm: Use DISAS_NORETURNRichard Henderson1-6/+8
2017-09-04target/arm: Make arm_cpu_dump_state() handle the M-profile XPSRPeter Maydell1-18/+40
2017-09-04target/arm: Tighten up Thumb decode where new v8M insns will bePeter Maydell1-9/+39
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+3
2017-07-19target/arm: optimize aarch32 rev16Aurelien Jarno1-2/+4
2017-07-17target/arm: use DISAS_EXIT for eret handlingAlex Bennée1-2/+4
2017-07-17target/arm: use gen_goto_tb for ISB handlingAlex Bennée1-2/+2
2017-07-17target/arm/translate: ensure gen_goto_tb sets exit flagsAlex Bennée1-1/+5
2017-07-17target/arm/translate: make DISAS_UPDATE match declared semanticsAlex Bennée1-3/+3
2017-06-05target/arm: optimize indirect branchesEmilio G. Cota1-9/+16
2017-06-05target/arm: optimize cross-page direct jumps in softmmuEmilio G. Cota1-1/+5
2017-06-02arm: Implement HFNMIENA support for M profile MPUPeter Maydell1-0/+1
2017-06-02arm: Use different ARMMMUIdx values for M profilePeter Maydell1-0/+3
2017-06-02arm: Add support for M profile CPUs having different MMU index semanticsPeter Maydell1-5/+5
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