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path: root/target/arm/translate.c
AgeCommit message (Expand)AuthorFilesLines
2019-09-27target/arm: handle A-profile semihosting at translate timeAlex Bennée1-4/+15
2019-09-27target/arm: handle M-profile semihosting at translate timeAlex Bennée1-1/+10
2019-09-05target/arm: Inline gen_bx_im into callersRichard Henderson1-19/+7
2019-09-05target/arm: Clean up disas_thumb_insnRichard Henderson1-25/+2
2019-09-05target/arm: Convert T16, long branchesRichard Henderson1-49/+36
2019-09-05target/arm: Convert T16, Unconditional branchRichard Henderson1-7/+2
2019-09-05target/arm: Convert T16, load (literal)Richard Henderson1-40/+2
2019-09-05target/arm: Convert T16, shift immediateRichard Henderson1-24/+2
2019-09-05target/arm: Convert T16, Miscellaneous 16-bit instructionsRichard Henderson1-77/+34
2019-09-05target/arm: Convert T16, Conditional branches, Supervisor callRichard Henderson1-23/+3
2019-09-05target/arm: Convert T16, push and popRichard Henderson1-71/+12
2019-09-05target/arm: Split gen_nop_hintRichard Henderson1-43/+24
2019-09-05target/arm: Convert T16, nop hintsRichard Henderson1-2/+1
2019-09-05target/arm: Convert T16, Reverse bytesRichard Henderson1-15/+3
2019-09-05target/arm: Convert T16, Change processor stateRichard Henderson1-46/+38
2019-09-05target/arm: Convert T16, extractRichard Henderson1-13/+1
2019-09-05target/arm: Convert T16 adjust sp (immediate)Richard Henderson1-13/+2
2019-09-05target/arm: Convert T16 add, compare, move (two high registers)Richard Henderson1-47/+2
2019-09-05target/arm: Convert T16 branch and exchangeRichard Henderson1-41/+29
2019-09-05target/arm: Convert T16 one low register and immediateRichard Henderson1-42/+2
2019-09-05target/arm: Convert T16 add/sub (3 low, 2 low and imm)Richard Henderson1-24/+2
2019-09-05target/arm: Convert T16 load/store multipleRichard Henderson1-39/+9
2019-09-05target/arm: Convert T16 add pc/sp (immediate)Richard Henderson1-11/+1
2019-09-05target/arm: Convert T16 load/store (immediate offset)Richard Henderson1-89/+5
2019-09-05target/arm: Convert T16 load/store (register offset)Richard Henderson1-49/+2
2019-09-05target/arm: Convert T16 data-processing (two low regs)Richard Henderson1-145/+7
2019-09-05target/arm: Add skeleton for T16 decodetreeRichard Henderson1-0/+6
2019-09-05target/arm: Simplify disas_arm_insnRichard Henderson1-53/+16
2019-09-05target/arm: Simplify disas_thumb2_insnRichard Henderson1-76/+3
2019-09-05target/arm: Convert TTRichard Henderson1-60/+30
2019-09-05target/arm: Convert SGRichard Henderson1-22/+29
2019-09-05target/arm: Convert Table BranchRichard Henderson1-23/+34
2019-09-05target/arm: Convert Unallocated memory hintRichard Henderson1-8/+0
2019-09-05target/arm: Convert PLI, PLD, PLDWRichard Henderson1-17/+20
2019-09-05target/arm: Convert SETENDRichard Henderson1-9/+13
2019-09-05target/arm: Convert CPS (privileged)Richard Henderson1-51/+40
2019-09-05target/arm: Convert Clear-Exclusive, BarriersRichard Henderson1-69/+58
2019-09-05target/arm: Convert RFE and SRSRichard Henderson1-89/+55
2019-09-05target/arm: Convert SVCRichard Henderson1-6/+13
2019-09-05target/arm: Convert B, BL, BLX (immediate)Richard Henderson1-75/+58
2019-09-05target/arm: Diagnose base == pc for LDM/STMRichard Henderson1-2/+3
2019-09-05target/arm: Diagnose too few registers in list for LDM/STMRichard Henderson1-8/+18
2019-09-05target/arm: Diagnose writeback register in list for LDM for v7Richard Henderson1-0/+9
2019-09-05target/arm: Convert LDM, STMRichard Henderson1-198/+230
2019-09-05target/arm: Convert MOVW, MOVTRichard Henderson1-56/+33
2019-09-05target/arm: Convert Signed multiply, signed and unsigned divideRichard Henderson1-272/+218
2019-09-05target/arm: Convert packing, unpacking, saturation, and reversalRichard Henderson1-309/+232
2019-09-05target/arm: Convert Parallel addition and subtractionRichard Henderson1-117/+112
2019-09-05target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDFRichard Henderson1-96/+105
2019-09-05target/arm: Diagnose UNPREDICTABLE ldrex/strex casesRichard Henderson1-2/+38