riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-10-20	target/arm: Enable TARGET_TB_PCREL	Richard Henderson	1	-1/+1
2022-10-20	target/arm: Change gen_exception_insn* to work on displacements	Richard Henderson	1	-3/+3
2022-06-10	target/arm: Introduce gen_exception_insn	Richard Henderson	1	-2/+1
2022-06-10	target/arm: Rename gen_exception_insn to gen_exception_insn_el	Richard Henderson	1	-8/+8
2022-04-22	target/arm: Use tcg_constant in translate-m-nocp.c	Richard Henderson	1	-7/+5
2021-09-21	target/arm: Add TB flag for "MVE insns not predicated"	Peter Maydell	1	-1/+7
2021-06-21	target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()	Peter Maydell	1	-8/+2
2021-06-21	target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access	Peter Maydell	1	-30/+72
2021-06-21	target/arm: Don't NOCP fault for FPCXT_NS accesses	Peter Maydell	1	-0/+514
2021-06-16	target/arm: Add handling for PSR.ECI/ICI	Peter Maydell	1	-0/+11
2021-06-16	target/arm: Handle VPR semantics in existing code	Peter Maydell	1	-1/+4
2021-05-10	target/arm: Split m-nocp trans functions into their own file	Peter Maydell	1	-0/+221