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path: root/target/arm/translate-a64.c
AgeCommit message (Expand)AuthorFilesLines
2018-06-29target/arm: Fix SVE system register access checksRichard Henderson1-3/+2
2018-06-29target/arm: Implement ARMv8.2-DotProdRichard Henderson1-0/+36
2018-06-29target/arm: Pass index to AdvSIMD FCMLA (indexed)Richard Henderson1-9/+12
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-3/+3
2018-05-18target/arm: Add SVE decode skeletonRichard Henderson1-1/+6
2018-05-18target/arm: Introduce translate-a64.hRichard Henderson1-97/+15
2018-05-17target/arm: convert conversion helpers to fpst/ahp_flagAlex Bennée1-7/+30
2018-05-15target/arm: Fix sqrt_f16 exception raisingAlex Bennée1-1/+2
2018-05-15target/arm: Implement FMOV (immediate) for fp16Alex Bennée1-3/+17
2018-05-15target/arm: Implement FCSEL for fp16Alex Bennée1-6/+25
2018-05-15target/arm: Implement FCMP for fp16Alex Bennée1-17/+71
2018-05-15target/arm: Implement FP data-processing (3 source) for fp16Richard Henderson1-0/+48
2018-05-15target/arm: Implement FP data-processing (2 source) for fp16Richard Henderson1-0/+65
2018-05-15target/arm: Introduce and use read_fp_hregRichard Henderson1-16/+14
2018-05-15target/arm: Implement FCVT (scalar, fixed-point) for fp16Richard Henderson1-2/+15
2018-05-15target/arm: Implement FCVT (scalar, integer) for fp16Richard Henderson1-16/+80
2018-05-15target/arm: Early exit after unallocated_encoding in disas_fp_int_convRichard Henderson1-1/+1
2018-05-15target/arm: Implement FMOV (general) for fp16Richard Henderson1-0/+21
2018-05-11Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell1-118/+364
2018-05-10target/arm: Clear SVE high bits for FMOVRichard Henderson1-12/+5
2018-05-10target/arm: Fix float16 to/from int16Richard Henderson1-2/+2
2018-05-10target/arm: Implement vector shifted FCVT for fp16Richard Henderson1-18/+45
2018-05-10target/arm: Implement vector shifted SCVF/UCVF for fp16Richard Henderson1-13/+20
2018-05-10target/arm: Implement CAS and CASPRichard Henderson1-3/+116
2018-05-10target/arm: Fill in disas_ldst_atomicRichard Henderson1-2/+36
2018-05-10target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decodeRichard Henderson1-43/+133
2018-05-10target/arm: Use new min/max expandersRichard Henderson1-32/+14
2018-05-09translator: merge max_insns into DisasContextBaseEmilio G. Cota1-5/+3
2018-05-04target/arm: Tidy condition in disas_simd_two_reg_miscRichard Henderson1-1/+5
2018-05-04target/arm: Tidy conditions in handle_vec_simd_shriRichard Henderson1-5/+1
2018-04-26target/arm: Allow EL change hooks to do IOAaron Lindsay1-0/+6
2018-03-23target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRKPeter Maydell1-2/+13
2018-03-23arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXITVictor Kamensky1-3/+3
2018-03-02target/arm: Decode aa64 armv8.3 fcmlaRichard Henderson1-8/+86
2018-03-02target/arm: Decode aa64 armv8.3 fcaddRichard Henderson1-1/+47
2018-03-02target/arm: Decode aa64 armv8.1 scalar/vector x indexed elementRichard Henderson1-0/+29
2018-03-02target/arm: Decode aa64 armv8.1 three same extraRichard Henderson1-0/+83
2018-03-02target/arm: Decode aa64 armv8.1 scalar three same extraRichard Henderson1-0/+84
2018-03-02target/arm: Refactor disas_simd_indexed size checksRichard Henderson1-31/+30
2018-03-02target/arm: Refactor disas_simd_indexed decodeRichard Henderson1-66/+59
2018-03-01arm/translate-a64: add all single op FP16 to handle_fp_1src_halfAlex Bennée1-0/+71
2018-03-01arm/translate-a64: implement simd_scalar_three_reg_same_fp16Alex Bennée1-0/+99
2018-03-01arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée1-26/+54
2018-03-01arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée1-10/+25
2018-03-01arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée1-0/+7
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée1-0/+5
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée1-0/+4
2018-03-01arm/translate-a64: add FP16 FRECPEAlex Bennée1-0/+8
2018-03-01arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée1-1/+15
2018-03-01arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée1-24/+90
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