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path: root/target/arm/translate-a64.c
AgeCommit message (Expand)AuthorFilesLines
2018-03-02target/arm: Decode aa64 armv8.3 fcmlaRichard Henderson1-8/+86
2018-03-02target/arm: Decode aa64 armv8.3 fcaddRichard Henderson1-1/+47
2018-03-02target/arm: Decode aa64 armv8.1 scalar/vector x indexed elementRichard Henderson1-0/+29
2018-03-02target/arm: Decode aa64 armv8.1 three same extraRichard Henderson1-0/+83
2018-03-02target/arm: Decode aa64 armv8.1 scalar three same extraRichard Henderson1-0/+84
2018-03-02target/arm: Refactor disas_simd_indexed size checksRichard Henderson1-31/+30
2018-03-02target/arm: Refactor disas_simd_indexed decodeRichard Henderson1-66/+59
2018-03-01arm/translate-a64: add all single op FP16 to handle_fp_1src_halfAlex Bennée1-0/+71
2018-03-01arm/translate-a64: implement simd_scalar_three_reg_same_fp16Alex Bennée1-0/+99
2018-03-01arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée1-26/+54
2018-03-01arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée1-10/+25
2018-03-01arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée1-0/+7
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée1-0/+5
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée1-0/+4
2018-03-01arm/translate-a64: add FP16 FRECPEAlex Bennée1-0/+8
2018-03-01arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée1-1/+15
2018-03-01arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée1-24/+90
2018-03-01arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16Alex Bennée1-23/+57
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée1-1/+84
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée1-5/+118
2018-03-01arm/translate-a64: initial decode for simd_two_reg_misc_fp16Alex Bennée1-0/+40
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée1-5/+21
2018-03-01arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexedAlex Bennée1-16/+66
2018-03-01arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16Alex Bennée1-75/+133
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée1-0/+6
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée1-0/+15
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée1-0/+15
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée1-0/+28
2018-03-01arm/translate-a64: initial decode for simd_three_reg_same_fp16Alex Bennée1-0/+73
2018-03-01arm/translate-a64: handle_3same_64 comment fixAlex Bennée1-2/+1
2018-03-01arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)Alex Bennée1-54/+88
2018-03-01target/arm/helper: pass explicit fpst to set_rmodeAlex Bennée1-13/+13
2018-03-01target/arm/cpu.h: add additional float_status flagsAlex Bennée1-24/+29
2018-02-15target/arm: Handle SVE registers when using clear_vec_highRichard Henderson1-100/+62
2018-02-15target/arm: Enforce access to ZCR_EL at translationRichard Henderson1-0/+16
2018-02-15target/arm: Enforce FP access to FPCR/FPSRRichard Henderson1-0/+3
2018-02-09target/arm: Add SVE state to TB->FLAGSRichard Henderson1-0/+2
2018-02-09target/arm: Expand vector registers for SVERichard Henderson1-4/+4
2018-02-09target/arm: implement SM4 instructionsArd Biesheuvel1-0/+8
2018-02-09target/arm: implement SM3 instructionsArd Biesheuvel1-3/+85
2018-02-09target/arm: implement SHA-3 instructionsArd Biesheuvel1-4/+144
2018-02-09target/arm: implement SHA-512 instructionsArd Biesheuvel1-0/+110
2018-02-08target/arm: Use vector infrastructure for aa64 orr/bic immediateRichard Henderson1-23/+5
2018-02-08target/arm: Use vector infrastructure for aa64 multipliesRichard Henderson1-25/+129
2018-02-08target/arm: Use vector infrastructure for aa64 comparesRichard Henderson1-34/+59
2018-02-08target/arm: Use vector infrastructure for aa64 constant shiftsRichard Henderson1-73/+346
2018-02-08target/arm: Use vector infrastructure for aa64 dup/moviRichard Henderson1-48/+33
2018-02-08target/arm: Use vector infrastructure for aa64 mov/not/negRichard Henderson1-6/+36
2018-02-08target/arm: Use vector infrastructure for aa64 add/sub/logicRichard Henderson1-72/+128
2018-01-25target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpersRichard Henderson1-17/+8
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