riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-08-31	target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS	Peter Maydell	1	-0/+9
2023-08-31	target/arm: properly document FEAT_CRC32	Alex Bennée	1	-1/+1
2023-08-31	target/arm: Implement FEAT_HPDS2 as a no-op	Richard Henderson	2	-2/+2
2023-08-31	target/arm: Apply access checks to neoverse-v1 special registers	Richard Henderson	1	-1/+2
2023-08-31	target/arm: Apply access checks to neoverse-n1 special registers	Richard Henderson	1	-9/+37
2023-08-31	target/arm: Introduce make_ccsidr64	Richard Henderson	1	-16/+32
2023-08-31	target/arm: Support more GM blocksizes	Richard Henderson	1	-8/+48
2023-08-31	target/arm: Allow cpu to configure GM blocksize	Richard Henderson	4	-18/+36
2023-08-24	target/arm: Use tcg_gen_negsetcond_*	Richard Henderson	2	-21/+13
2023-08-22	target/arm: Fix 64-bit SSRA	Richard Henderson	1	-1/+1
2023-08-22	target/arm: Fix SME ST1Q	Richard Henderson	1	-1/+1
2023-07-31	target/arm/tcg: Don't build AArch64 decodetree files for qemu-system-arm	Peter Maydell	1	-3/+7
2023-07-31	target/arm: Avoid writing to constant TCGv in trans_CSEL()	Peter Maydell	1	-7/+8
2023-07-31	target/arm: Fix MemOp for STGP	Richard Henderson	1	-3/+18
2023-07-25	arm: spelling fixes	Michael Tokarev	6	-8/+8
2023-07-09	target/arm: Use aesdec_IMC	Richard Henderson	1	-19/+14
2023-07-09	target/arm: Use aesenc_MC	Richard Henderson	1	-1/+14
2023-07-09	target/arm: Use aesdec_ISB_ISR_AK	Richard Henderson	1	-21/+16
2023-07-09	target/arm: Use aesenc_SB_SR_AK	Richard Henderson	1	-1/+23
2023-07-08	target/arm: Demultiplex AESE and AESMC	Richard Henderson	5	-27/+39
2023-07-08	target/arm: Move aesmc and aesimc tables to crypto/aes.c	Richard Henderson	1	-138/+5
2023-07-06	target/arm: Define neoverse-v1	Peter Maydell	1	-0/+128
2023-07-06	target/arm: Fix SME full tile indexing	Richard Henderson	1	-6/+18
2023-07-03	plugins: force slow path when plugins instrument memory ops	Alex Bennée	1	-4/+0
2023-06-23	target/arm: Fix sve predicate store, 8 <= VQ <= 15	Richard Henderson	1	-1/+1
2023-06-23	target/arm: Add cpu properties for enabling FEAT_RME	Richard Henderson	1	-0/+53
2023-06-23	target/arm: Implement GPC exceptions	Richard Henderson	1	-3/+93
2023-06-20	meson: Replace softmmu_ss -> system_ss	Philippe Mathieu-Daudé	1	-1/+1
2023-06-19	target/arm: Convert load/store tags insns to decodetree	Peter Maydell	2	-177/+190
2023-06-19	target/arm: Convert load/store single structure to decodetree	Peter Maydell	2	-108/+127
2023-06-19	target/arm: Convert load/store (multiple structures) to decodetree	Peter Maydell	2	-108/+128
2023-06-19	target/arm: Convert LDAPR/STLR (imm) to decodetree	Peter Maydell	2	-84/+54
2023-06-19	target/arm: Convert load (pointer auth) insns to decodetree	Peter Maydell	2	-67/+23
2023-06-19	target/arm: Convert atomic memory ops to decodetree	Peter Maydell	2	-98/+70
2023-06-19	target/arm: Convert LDR/STR reg+reg to decodetree	Peter Maydell	2	-87/+98
2023-06-19	target/arm: Convert LDR/STR with 12-bit immediate to decodetree	Peter Maydell	2	-88/+41
2023-06-19	target/arm: Convert ld/st reg+imm9 insns to decodetree	Peter Maydell	2	-118/+149
2023-06-19	target/arm: Convert load/store-pair to decodetree	Peter Maydell	2	-196/+249
2023-06-19	target/arm: Convert load reg (literal) group to decodetree	Peter Maydell	2	-54/+35
2023-06-19	target/arm: Convert LDXP, STXP, CASP, CAS to decodetree	Peter Maydell	2	-76/+50
2023-06-19	target/arm: Convert load/store exclusive and ordered to decodetree	Peter Maydell	2	-62/+103
2023-06-19	target/arm: Convert exception generation instructions to decodetree	Peter Maydell	2	-106/+76
2023-06-19	target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree	Peter Maydell	2	-28/+14
2023-06-19	target/arm: Convert MSR (immediate) to decodetree	Peter Maydell	2	-115/+123
2023-06-19	target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree	Peter Maydell	2	-27/+32
2023-06-19	target/arm: Convert barrier insns to decodetree	Peter Maydell	2	-53/+46
2023-06-19	target/arm: Convert hint instruction space to decodetree	Peter Maydell	2	-123/+185
2023-06-19	target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores	Peter Maydell	1	-4/+6
2023-06-19	target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode	Peter Maydell	1	-1/+1
2023-06-19	target/arm: Return correct result for LDG when ATA=0	Peter Maydell	1	-1/+5