| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-06-06 | target/arm: Enable FEAT_LSE2 for -cpu max | Richard Henderson | 1 | -0/+1 |
| 2023-06-06 | target/arm: Move mte check for store-exclusive | Richard Henderson | 1 | -6/+36 |
| 2023-06-06 | target/arm: Relax ordered/atomic alignment checks for LSE2 | Richard Henderson | 3 | -26/+104 |
| 2023-06-06 | target/arm: Add SCTLR.nAA to TBFLAG_A64 | Richard Henderson | 3 | -0/+9 |
| 2023-06-06 | target/arm: Check alignment in helper_mte_check | Richard Henderson | 2 | -0/+20 |
| 2023-06-06 | target/arm: Pass single_memop to gen_mte_checkN | Richard Henderson | 3 | -15/+22 |
| 2023-06-06 | target/arm: Pass memop to gen_mte_check1* | Richard Henderson | 3 | -42/+49 |
| 2023-06-06 | target/arm: Hoist finalize_memop out of do_fp_{ld, st} | Richard Henderson | 1 | -20/+23 |
| 2023-06-06 | target/arm: Hoist finalize_memop out of do_gpr_{ld, st} | Richard Henderson | 1 | -26/+35 |
| 2023-06-06 | target/arm: Load/store integer pair with one tcg operation | Richard Henderson | 1 | -15/+55 |
| 2023-06-06 | target/arm: Sink gen_mte_check1 into load/store_exclusive | Richard Henderson | 1 | -23/+21 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r | Richard Henderson | 1 | -25/+70 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G | Richard Henderson | 1 | -7/+10 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} | Richard Henderson | 2 | -24/+35 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_ld_i128 for LDXP | Richard Henderson | 1 | -11/+20 |
| 2023-06-06 | target/arm: Introduce finalize_memop_{atom,pair} | Richard Henderson | 3 | -5/+37 |
| 2023-06-05 | target/arm: Add missing include of exec/exec-all.h | Richard Henderson | 1 | -0/+1 |
| 2023-06-05 | target/arm: Tidy helpers for translation | Richard Henderson | 9 | -46/+9 |
| 2023-06-05 | accel/tcg: Introduce translator_io_start | Richard Henderson | 5 | -32/+17 |
| 2023-06-05 | tcg: Split helper-proto.h | Richard Henderson | 1 | -0/+1 |
| 2023-06-05 | tcg: Split helper-gen.h | Richard Henderson | 1 | -5/+3 |
| 2023-06-05 | tcg: Pass TCGHelperInfo to tcg_gen_callN | Richard Henderson | 1 | -0/+3 |
| 2023-06-05 | target/arm: Include helper-gen.h in translator.h | Richard Henderson | 5 | -7/+1 |
| 2023-05-30 | target/arm: Explicitly select short-format FSR for M-profile | Peter Maydell | 1 | -2/+11 |
| 2023-05-23 | accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu | Richard Henderson | 1 | -2/+2 |
| 2023-05-18 | target/arm: Convert ERET, ERETAA, ERETAB to decodetree | Peter Maydell | 2 | -108/+63 |
| 2023-05-18 | target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree | Peter Maydell | 2 | -58/+43 |
| 2023-05-18 | target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree | Peter Maydell | 2 | -55/+84 |
| 2023-05-18 | target/arm: Convert BR, BLR, RET to decodetree | Peter Maydell | 2 | -6/+54 |
| 2023-05-18 | target/arm: Convert conditional branch insns to decodetree | Peter Maydell | 2 | -24/+8 |
| 2023-05-18 | target/arm: Convert TBZ, TBNZ to decodetree | Peter Maydell | 2 | -20/+11 |
| 2023-05-18 | target/arm: Convert CBZ, CBNZ to decodetree | Peter Maydell | 2 | -20/+11 |
| 2023-05-18 | target/arm: Convert unconditional branch immediate to decodetree | Peter Maydell | 2 | -19/+19 |
| 2023-05-18 | target/arm: Convert Extract instructions to decodetree | Peter Maydell | 2 | -63/+34 |
| 2023-05-18 | target/arm: Convert Bitfield to decodetree | Richard Henderson | 2 | -57/+88 |
| 2023-05-18 | target/arm: Convert Move wide (immediate) to decodetree | Richard Henderson | 2 | -43/+41 |
| 2023-05-18 | target/arm: Convert Logical (immediate) to decodetree | Richard Henderson | 2 | -64/+43 |
| 2023-05-18 | target/arm: Replace bitmask64 with MAKE_64BIT_MASK | Richard Henderson | 1 | -9/+2 |
| 2023-05-18 | target/arm: Convert Add/subtract (immediate with tags) to decodetree | Richard Henderson | 2 | -27/+19 |
| 2023-05-18 | target/arm: Convert Add/subtract (immediate) to decodetree | Richard Henderson | 3 | -53/+42 |
| 2023-05-18 | target/arm: Split gen_add_CC and gen_sub_CC | Richard Henderson | 1 | -60/+79 |
| 2023-05-18 | target/arm: Convert PC-rel addressing to decodetree | Richard Henderson | 2 | -24/+27 |
| 2023-05-18 | target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoder | Peter Maydell | 1 | -16/+4 |
| 2023-05-18 | target/arm: Create decodetree skeleton for A64 | Peter Maydell | 3 | -7/+32 |
| 2023-05-18 | target/arm: Split out disas_a64_legacy | Richard Henderson | 1 | -38/+44 |
| 2023-05-18 | target/arm: Fix vd == vm overlap in sve_ldff1_z | Richard Henderson | 1 | -0/+6 |
| 2023-05-12 | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check | Peter Maydell | 1 | -3/+3 |
| 2023-05-12 | target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ | Richard Henderson | 4 | -0/+3952 |
| 2023-05-12 | target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ | Richard Henderson | 3 | -0/+436 |
| 2023-05-02 | target/arm: Define and use new load_cpu_field_low32() | Peter Maydell | 1 | -2/+2 |
