| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-06-06 | target/arm: Move mte check for store-exclusive | Richard Henderson | 1 | -6/+36 |
| 2023-06-06 | target/arm: Relax ordered/atomic alignment checks for LSE2 | Richard Henderson | 1 | -26/+94 |
| 2023-06-06 | target/arm: Add SCTLR.nAA to TBFLAG_A64 | Richard Henderson | 1 | -0/+1 |
| 2023-06-06 | target/arm: Check alignment in helper_mte_check | Richard Henderson | 1 | -0/+2 |
| 2023-06-06 | target/arm: Pass single_memop to gen_mte_checkN | Richard Henderson | 1 | -12/+19 |
| 2023-06-06 | target/arm: Pass memop to gen_mte_check1* | Richard Henderson | 1 | -38/+44 |
| 2023-06-06 | target/arm: Hoist finalize_memop out of do_fp_{ld, st} | Richard Henderson | 1 | -20/+23 |
| 2023-06-06 | target/arm: Hoist finalize_memop out of do_gpr_{ld, st} | Richard Henderson | 1 | -26/+35 |
| 2023-06-06 | target/arm: Load/store integer pair with one tcg operation | Richard Henderson | 1 | -15/+55 |
| 2023-06-06 | target/arm: Sink gen_mte_check1 into load/store_exclusive | Richard Henderson | 1 | -23/+21 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G | Richard Henderson | 1 | -7/+10 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} | Richard Henderson | 1 | -24/+11 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_ld_i128 for LDXP | Richard Henderson | 1 | -11/+20 |
| 2023-06-06 | target/arm: Introduce finalize_memop_{atom,pair} | Richard Henderson | 1 | -0/+2 |
| 2023-06-05 | target/arm: Tidy helpers for translation | Richard Henderson | 1 | -10/+3 |
| 2023-06-05 | accel/tcg: Introduce translator_io_start | Richard Henderson | 1 | -13/+10 |
| 2023-06-05 | target/arm: Include helper-gen.h in translator.h | Richard Henderson | 1 | -2/+0 |
| 2023-05-18 | target/arm: Convert ERET, ERETAA, ERETAB to decodetree | Peter Maydell | 1 | -108/+55 |
| 2023-05-18 | target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree | Peter Maydell | 1 | -58/+39 |
| 2023-05-18 | target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree | Peter Maydell | 1 | -55/+77 |
| 2023-05-18 | target/arm: Convert BR, BLR, RET to decodetree | Peter Maydell | 1 | -6/+49 |
| 2023-05-18 | target/arm: Convert conditional branch insns to decodetree | Peter Maydell | 1 | -24/+6 |
| 2023-05-18 | target/arm: Convert TBZ, TBNZ to decodetree | Peter Maydell | 1 | -20/+5 |
| 2023-05-18 | target/arm: Convert CBZ, CBNZ to decodetree | Peter Maydell | 1 | -20/+6 |
| 2023-05-18 | target/arm: Convert unconditional branch immediate to decodetree | Peter Maydell | 1 | -19/+10 |
| 2023-05-18 | target/arm: Convert Extract instructions to decodetree | Peter Maydell | 1 | -63/+27 |
| 2023-05-18 | target/arm: Convert Bitfield to decodetree | Richard Henderson | 1 | -57/+75 |
| 2023-05-18 | target/arm: Convert Move wide (immediate) to decodetree | Richard Henderson | 1 | -43/+28 |
| 2023-05-18 | target/arm: Convert Logical (immediate) to decodetree | Richard Henderson | 1 | -64/+28 |
| 2023-05-18 | target/arm: Replace bitmask64 with MAKE_64BIT_MASK | Richard Henderson | 1 | -9/+2 |
| 2023-05-18 | target/arm: Convert Add/subtract (immediate with tags) to decodetree | Richard Henderson | 1 | -27/+11 |
| 2023-05-18 | target/arm: Convert Add/subtract (immediate) to decodetree | Richard Henderson | 1 | -53/+20 |
| 2023-05-18 | target/arm: Split gen_add_CC and gen_sub_CC | Richard Henderson | 1 | -60/+79 |
| 2023-05-18 | target/arm: Convert PC-rel addressing to decodetree | Richard Henderson | 1 | -24/+14 |
| 2023-05-18 | target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoder | Peter Maydell | 1 | -16/+4 |
| 2023-05-18 | target/arm: Create decodetree skeleton for A64 | Peter Maydell | 1 | -7/+11 |
| 2023-05-18 | target/arm: Split out disas_a64_legacy | Richard Henderson | 1 | -38/+44 |
| 2023-03-13 | target/arm: Avoid tcg_const_ptr in handle_rev | Richard Henderson | 1 | -11/+15 |
| 2023-03-13 | target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn | Richard Henderson | 1 | -2/+6 |
| 2023-03-13 | target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn | Richard Henderson | 1 | -20/+21 |
| 2023-03-13 | target/arm: Create gen_set_rmode, gen_restore_rmode | Richard Henderson | 1 | -28/+19 |
| 2023-03-13 | target/arm: Consistently use ARMFPRounding during translation | Richard Henderson | 1 | -8/+8 |
| 2023-03-13 | target/arm: Use rmode >= 0 for need_rmode | Richard Henderson | 1 | -28/+6 |
| 2023-03-05 | target/arm: Drop tcg_temp_free from translator-a64.c | Richard Henderson | 1 | -457/+11 |
| 2023-03-05 | target/arm: Drop new_tmp_a64_zero | Richard Henderson | 1 | -23/+18 |
| 2023-03-05 | target/arm: Drop new_tmp_a64 | Richard Henderson | 1 | -25/+20 |
| 2023-03-05 | target/arm: Drop DisasContext.tmp_a64 | Richard Henderson | 1 | -24/+1 |
| 2023-03-05 | target/arm: Remove arm_free_cc, a64_free_cc | Richard Henderson | 1 | -13/+4 |
| 2023-03-05 | accel/tcg: Remove translator_loop_temp_check | Richard Henderson | 1 | -2/+0 |
| 2023-03-01 | target/arm: Drop copies in gen_sve_{ldr,str} | Richard Henderson | 1 | -6/+0 |
