| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-07-11 | target/arm: Implement REVD | Richard Henderson | 1 | -0/+16 |
| 2022-07-11 | target/arm: Implement SME MOVA | Richard Henderson | 1 | -0/+12 |
| 2022-07-07 | target/arm: Record tagged bit for user-only in sve_probe_page | Richard Henderson | 1 | -0/+3 |
| 2022-07-07 | target/arm: Fix MTE check in sve_ldnfff1_r | Richard Henderson | 1 | -1/+1 |
| 2022-06-08 | target/arm: Move expand_pred_h to vec_internal.h | Richard Henderson | 1 | -29/+0 |
| 2022-06-08 | target/arm: Move expand_pred_b to vec_internal.h | Richard Henderson | 1 | -9/+0 |
| 2022-06-08 | target/arm: Export sve contiguous ldst support functions | Richard Henderson | 1 | -70/+17 |
| 2022-06-08 | target/arm: Split out load/store primitives to sve_ldst_internal.h | Richard Henderson | 1 | -106/+1 |
| 2022-05-30 | target/arm: Move sve zip high_ofs into simd_data | Richard Henderson | 1 | -2/+4 |
| 2022-04-06 | Replace config-time define HOST_WORDS_BIGENDIAN | Marc-André Lureau | 1 | -2/+2 |
| 2022-03-25 | target/arm: Fix sve_ld1_z and sve_st1_z vs MMIO | Richard Henderson | 1 | -2/+8 |
| 2021-11-02 | target/arm: Fixup comment re handle_cpu_signal | Richard Henderson | 1 | -1/+1 |
| 2021-06-16 | bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations | Peter Maydell | 1 | -20/+0 |
| 2021-06-16 | target/arm: Move expand_pred_b() data to vec_helper.c | Peter Maydell | 1 | -99/+4 |
| 2021-06-16 | target/arm: Provide and use H8 and H1_8 macros | Peter Maydell | 1 | -129/+129 |
| 2021-06-03 | target/arm: Implement vector float32 to bfloat16 conversion | Richard Henderson | 1 | -0/+2 |
| 2021-05-25 | target/arm: Move endian adjustment macros to vec_internal.h | Richard Henderson | 1 | -16/+0 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise shift immediate | Stephen Long | 1 | -0/+35 |
| 2021-05-25 | target/arm: Implement 128-bit ZIP, UZP, TRN | Richard Henderson | 1 | -8/+21 |
| 2021-05-25 | target/arm: Implement SVE2 FLOGB | Stephen Long | 1 | -0/+88 |
| 2021-05-25 | target/arm: Implement SVE2 FCVTLT | Stephen Long | 1 | -0/+23 |
| 2021-05-25 | target/arm: Implement SVE2 FCVTNT | Richard Henderson | 1 | -0/+20 |
| 2021-05-25 | target/arm: Implement SVE2 TBL, TBX | Stephen Long | 1 | -19/+71 |
| 2021-05-25 | target/arm: Implement SVE2 complex integer dot product | Richard Henderson | 1 | -0/+99 |
| 2021-05-25 | target/arm: Implement SVE2 complex integer multiply-add (indexed) | Richard Henderson | 1 | -0/+28 |
| 2021-05-25 | target/arm: Implement SVE2 integer multiply long (indexed) | Richard Henderson | 1 | -0/+6 |
| 2021-05-25 | target/arm: Implement SVE2 multiply-add long (indexed) | Richard Henderson | 1 | -0/+16 |
| 2021-05-25 | target/arm: Implement SVE2 saturating multiply (indexed) | Richard Henderson | 1 | -0/+20 |
| 2021-05-25 | target/arm: Implement SVE2 saturating multiply-add (indexed) | Richard Henderson | 1 | -0/+30 |
| 2021-05-25 | target/arm: Implement SVE2 saturating multiply-add high (indexed) | Richard Henderson | 1 | -0/+36 |
| 2021-05-25 | target/arm: Implement SVE2 FMMLA | Stephen Long | 1 | -0/+74 |
| 2021-05-25 | target/arm: Implement SVE2 XAR | Richard Henderson | 1 | -0/+39 |
| 2021-05-25 | target/arm: Implement SVE2 HISTCNT, HISTSEG | Stephen Long | 1 | -0/+131 |
| 2021-05-25 | target/arm: Implement SVE2 RSUBHNB, RSUBHNT | Stephen Long | 1 | -0/+10 |
| 2021-05-25 | target/arm: Implement SVE2 SUBHNB, SUBHNT | Stephen Long | 1 | -0/+10 |
| 2021-05-25 | target/arm: Implement SVE2 RADDHNB, RADDHNT | Stephen Long | 1 | -0/+10 |
| 2021-05-25 | target/arm: Implement SVE2 ADDHNB, ADDHNT | Stephen Long | 1 | -0/+36 |
| 2021-05-25 | target/arm: Implement SVE2 complex integer multiply-add | Richard Henderson | 1 | -0/+46 |
| 2021-05-25 | target/arm: Implement SVE2 integer multiply-add long | Richard Henderson | 1 | -0/+18 |
| 2021-05-25 | target/arm: Implement SVE2 saturating multiply-add long | Richard Henderson | 1 | -0/+30 |
| 2021-05-25 | target/arm: Implement SVE2 MATCH, NMATCH | Stephen Long | 1 | -0/+64 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise ternary operations | Richard Henderson | 1 | -0/+50 |
| 2021-05-25 | target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS | Richard Henderson | 1 | -1/+37 |
| 2021-05-25 | target/arm: Implement SVE2 SQSHRN, SQRSHRN | Richard Henderson | 1 | -0/+24 |
| 2021-05-25 | target/arm: Implement SVE2 UQSHRN, UQRSHRN | Richard Henderson | 1 | -0/+24 |
| 2021-05-25 | target/arm: Implement SVE2 SQSHRUN, SQRSHRUN | Richard Henderson | 1 | -0/+35 |
| 2021-05-25 | target/arm: Implement SVE2 SHRN, RSHRN | Richard Henderson | 1 | -2/+52 |
| 2021-05-25 | target/arm: Implement SVE2 floating-point pairwise | Stephen Long | 1 | -0/+46 |
| 2021-05-25 | target/arm: Implement SVE2 saturating extract narrow | Richard Henderson | 1 | -0/+56 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract long with carry | Richard Henderson | 1 | -0/+34 |
