riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-08-06	target/arm: Add dummy needed functions to M profile vmstate subsections	Peter Maydell	1	-0/+3
2018-02-15	target/arm: Implement v8M MSPLIM and PSPLIM registers	Peter Maydell	1	-0/+21
2018-02-15	target/arm: Migrate v7m.other_sp	Peter Maydell	1	-0/+11
2018-02-15	target/arm: Add AIRCR to vmstate struct	Peter Maydell	1	-0/+4
2018-02-15	hw/intc/armv7m_nvic: Implement SCR	Peter Maydell	1	-0/+12
2018-02-15	hw/intc/armv7m_nvic: Implement cache ID registers	Peter Maydell	1	-0/+36
2018-02-09	target/arm: Add SVE to migration state	Richard Henderson	1	-0/+53
2018-02-09	target/arm: Expand vector registers for SVE	Richard Henderson	1	-1/+34
2018-01-25	target/arm: Change the type of vfp.regs	Richard Henderson	1	-1/+1
2017-10-06	nvic: Implement Security Attribution Unit registers	Peter Maydell	1	-0/+14
2017-10-06	target/arm: Add new-in-v8M SFSR and SFAR	Peter Maydell	1	-0/+2
2017-09-27	migration: pre_save return int	Dr. David Alan Gilbert	1	-1/+3
2017-09-07	target/arm: Implement BXNS, and banked stack pointers	Peter Maydell	1	-0/+2
2017-09-07	target/arm: Make CFSR register banked for v8M	Peter Maydell	1	-1/+2
2017-09-07	target/arm: Make MMFAR banked for v8M	Peter Maydell	1	-1/+2
2017-09-07	target/arm: Make CCR register banked for v8M	Peter Maydell	1	-1/+2
2017-09-07	target/arm: Make MPU_CTRL register banked for v8M	Peter Maydell	1	-1/+2
2017-09-07	target/arm: Make MPU_RNR register banked for v8M	Peter Maydell	1	-2/+11
2017-09-07	target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M	Peter Maydell	1	-4/+8
2017-09-07	target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M	Peter Maydell	1	-2/+4
2017-09-07	target/arm: Make VTOR register banked for v8M	Peter Maydell	1	-1/+2
2017-09-07	target/arm: Make CONTROL register banked for v8M	Peter Maydell	1	-1/+2
2017-09-07	target/arm: Make FAULTMASK register banked for v8M	Peter Maydell	1	-2/+3
2017-09-07	target/arm: Make PRIMASK register banked for v8M	Peter Maydell	1	-2/+7
2017-09-07	target/arm: Make BASEPRI register banked for v8M	Peter Maydell	1	-1/+2
2017-09-07	target/arm: Add state field, feature bit and migration for v8M secure state	Peter Maydell	1	-0/+20
2017-09-07	target/arm: Implement ARMv8M's PMSAv8 registers	Peter Maydell	1	-1/+28
2017-09-04	target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR	Peter Maydell	1	-15/+34
2017-09-04	target/arm: Don't store M profile PRIMASK and FAULTMASK in daif	Peter Maydell	1	-0/+33
2017-07-31	target/arm: Migrate MPU_RNR register state for M profile cores	Peter Maydell	1	-0/+28
2017-07-31	target/arm: Rename cp15.c6_rgnr to pmsav7.rnr	Peter Maydell	1	-1/+1
2017-06-02	arm: add MPU support to M profile CPUs	Michael Davidsaver	1	-2/+3
2017-06-02	arm: Clean up handling of no-MPU PMSA CPUs	Peter Maydell	1	-1/+1
2017-02-24	target-arm/powerctl: defer cpu reset work to CPU context	Alex Bennée	1	-1/+40
2017-01-27	armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR	Peter Maydell	1	-2/+8
2017-01-27	armv7m: Fix reads of CONTROL register bit 1	Michael Davidsaver	1	-4/+2
2017-01-24	migration: extend VMStateInfo	Jianjun Duan	1	-4/+10
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+333