aboutsummaryrefslogtreecommitdiff
path: root/target/arm/internals.h
AgeCommit message (Expand)AuthorFilesLines
2021-11-02target/arm: Implement arm_cpu_record_sigbusRichard Henderson1-0/+2
2021-11-02target/arm: Implement arm_cpu_record_sigsegvRichard Henderson1-0/+6
2021-09-30target/arm: Move gdbstub related code out of helper.cPeter Maydell1-0/+7
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson1-1/+1
2021-09-20arm: Move PMC register definitions to internals.hAlexander Graf1-0/+44
2021-07-27target/arm: Export aarch64_sve_zcr_get_valid_lenRichard Henderson1-0/+10
2021-07-21target/arm: Implement debug_check_breakpointRichard Henderson1-0/+3
2021-06-21target/arm: Implement MVE VLDR/VSTR (non-widening forms)Peter Maydell1-0/+11
2021-04-30target/arm: Rename mte_probe1 to mte_probeRichard Henderson1-1/+1
2021-04-30target/arm: Merge mte_check1, mte_checkNRichard Henderson1-4/+1
2021-04-30target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1Richard Henderson1-2/+2
2021-03-05target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran1-0/+6
2021-02-18exec: Move TranslationBlock typedef to qemu/typedefs.hRichard Henderson1-2/+1
2021-02-16target/arm: Split out syndrome.h from internals.hRichard Henderson1-244/+1
2021-02-16target/arm: Use the proper TBI settings for linux-userRichard Henderson1-2/+2
2021-02-11target/arm: Add support for FEAT_DIT, Data Independent TimingRebecca Cran1-0/+6
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-0/+6
2021-01-19target/arm: Introduce PREDDESC field definitionsRichard Henderson1-0/+9
2021-01-19target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont1-0/+2
2021-01-19target/arm: secure stage 2 translation regimeRémi Denis-Courmont1-0/+22
2021-01-19target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont1-0/+12
2020-10-20target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11Richard Henderson1-4/+5
2020-06-26target/arm: Always pass cacheattr to get_phys_addrRichard Henderson1-1/+2
2020-06-26target/arm: Add mte helpers for sve scalar + int loadsRichard Henderson1-0/+6
2020-06-26target/arm: Implement helper_mte_checkNRichard Henderson1-0/+2
2020-06-26target/arm: Implement helper_mte_check1Richard Henderson1-0/+48
2020-06-26target/arm: Add gen_mte_check1Richard Henderson1-0/+8
2020-06-26target/arm: Move regime_tcr to internals.hRichard Henderson1-0/+9
2020-06-26target/arm: Move regime_el to internals.hRichard Henderson1-0/+36
2020-06-26target/arm: Implement the ADDG, SUBG instructionsRichard Henderson1-0/+9
2020-06-26target/arm: Implement the IRG instructionRichard Henderson1-0/+5
2020-06-26target/arm: Add MTE bits to tb_flagsRichard Henderson1-0/+18
2020-06-26target/arm: Add MTE system registersRichard Henderson1-0/+9
2020-05-14target-arm: kvm64: handle SIGBUS signal from kernel or KVMDongjiu Geng1-2/+3
2020-05-11target/arm: Remove sve_memopidxRichard Henderson1-5/+0
2020-03-05target/arm: Introduce core_to_aa64_mmu_idxRichard Henderson1-0/+6
2020-02-21target/arm: Move DBGDIDR into ARMISARegistersPeter Maydell1-3/+3
2020-02-21target/arm: Stop assuming DBGDIDR always existsPeter Maydell1-0/+42
2020-02-21target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registersPeter Maydell1-1/+1
2020-02-21target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbidRichard Henderson1-3/+0
2020-02-13target/arm: Update MSR access to UAORichard Henderson1-0/+3
2020-02-13target/arm: Enforce PAN semantics in get_S1protRichard Henderson1-0/+13
2020-02-13target/arm: Update MSR access for PANRichard Henderson1-0/+6
2020-02-13target/arm: Introduce aarch64_pstate_valid_maskRichard Henderson1-0/+12
2020-02-13target/arm: Mask CPSR_J when Jazelle is not enabledRichard Henderson1-1/+4
2020-02-13target/arm: Split out aarch32_cpsr_valid_maskRichard Henderson1-0/+21
2020-02-13target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabledRichard Henderson1-0/+9
2020-02-13target/arm: Add arm_mmu_idx_is_stage1_of_2Richard Henderson1-0/+18
2020-02-07target/arm: Add regime_has_2_rangesRichard Henderson1-0/+18
2020-02-07target/arm: Reorganize ARMMMUIdxRichard Henderson1-0/+35