riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-02-15	target/arm: Enforce access to ZCR_EL at translation	Richard Henderson	1	-0/+6
2018-01-16	target/arm: Handle page table walk load failures correctly	Peter Maydell	1	-0/+10
2017-12-13	target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill()	Peter Maydell	1	-1/+1
2017-12-13	target/arm: Provide fault type enum and FSR conversion functions	Peter Maydell	1	-0/+185
2017-12-13	target/arm: Split M profile MNegPri mmu index into user and priv	Peter Maydell	1	-2/+4
2017-10-31	fix WFI/WFE length in syndrome register	Stefano Stabellini	1	-1/+2
2017-10-12	target/arm: Implement secure function return	Peter Maydell	1	-0/+7
2017-10-12	target/arm: Implement BLXNS	Peter Maydell	1	-0/+1
2017-10-06	target/arm: Implement security attribute lookups for memory accesses	Peter Maydell	1	-0/+15
2017-09-14	target/arm: Add and use defines for EXCRET constants	Peter Maydell	1	-0/+10
2017-09-14	target/arm: Clear exclusive monitor on v7M reset, exception entry/exit	Peter Maydell	1	-0/+10
2017-09-07	target/arm: Implement new do_transaction_failed hook	Peter Maydell	1	-0/+10
2017-09-07	target/arm: Move regime_is_secure() to target/arm/internals.h	Peter Maydell	1	-0/+26
2017-09-04	target/arm: Allow deliver_fault() caller to specify EA bit	Peter Maydell	1	-0/+2
2017-09-04	target/arm: Use MMUAccessType enum rather than int	Peter Maydell	1	-1/+2
2017-04-20	arm: Move excnames[] array into arm_log_exceptions()	Peter Maydell	1	-23/+0
2017-04-20	target/arm: Add missing entries to excnames[] for log strings	Peter Maydell	1	-0/+2
2017-02-07	arm: Correctly handle watchpoints for BE32 CPUs	Julian Brown	1	-0/+5
2017-01-27	armv7m: Fix reads of CONTROL register bit 1	Michael Davidsaver	1	-0/+7
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+489