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path: root/target/arm/helper.c
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2021-07-27target/arm: Export aarch64_sve_zcr_get_valid_lenRichard Henderson1-2/+2
2021-07-27target/arm: Correctly bound length in sve_zcr_get_valid_lenRichard Henderson1-1/+3
2021-07-18target/arm: Fix offsets for TTBCRRichard Henderson1-4/+7
2021-07-09target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRinthnick@vmware.com1-3/+13
2021-05-25target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2Richard Henderson1-2/+1
2021-05-25target/arm: Add support for FEAT_TLBIOSRebecca Cran1-0/+43
2021-05-25target/arm: Add support for FEAT_TLBIRANGERebecca Cran1-0/+281
2021-05-10target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write()Peter Maydell1-1/+1
2021-04-30target/arm: Add ALIGN_MEM to TBFLAG_ANYRichard Henderson1-2/+17
2021-04-30target/arm: Move mode specific TB flags to tb->cs_baseRichard Henderson1-4/+6
2021-04-30target/arm: Introduce CPUARMTBFlagsRichard Henderson1-22/+26
2021-04-30target/arm: Add wrapper macros for accessing tbflagsRichard Henderson1-46/+39
2021-04-30target/arm: Rename TBFLAG_ANY, PSTATE_SSRichard Henderson1-2/+2
2021-04-30target/arm: Rename TBFLAG_A32, SCTLR_BRichard Henderson1-1/+1
2021-04-06Revert "target/arm: Make number of counters in PMCR follow the CPU"Peter Maydell1-17/+12
2021-03-30target/arm: Make number of counters in PMCR follow the CPUPeter Maydell1-12/+17
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé1-2/+2
2021-03-05target/arm: Use TCF0 and TFSRE0 for unprivileged tag checksPeter Collingbourne1-1/+1
2021-03-05target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran1-0/+37
2021-02-11target/arm: Correctly initialize MDCR_EL2.HPMNDaniel Müller1-5/+4
2021-02-11target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstateRebecca Cran1-6/+18
2021-02-11target/arm: Add support for FEAT_DIT, Data Independent TimingRebecca Cran1-0/+22
2021-02-11target/arm: Fix SCR RES1 handlingMike Nawrocki1-2/+14
2021-02-05target/arm: do not use cc->do_interrupt for KVM directlyClaudio Fontana1-0/+4
2021-01-29target/arm: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé1-1/+1
2021-01-29target/arm: Conditionalize DBGDIDRRichard Henderson1-6/+15
2021-01-29target/arm: Implement ID_PFR2Richard Henderson1-2/+2
2021-01-19target/arm: refactor vae1_tlbmask()Rémi Denis-Courmont1-14/+11
2021-01-19target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont1-3/+16
2021-01-19target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont1-0/+6
2021-01-19target/arm: secure stage 2 translation regimeRémi Denis-Courmont1-24/+54
2021-01-19target/arm: generalize 2-stage page-walk conditionRémi Denis-Courmont1-7/+6
2021-01-19target/arm: translate NS bit in page-walksRémi Denis-Courmont1-0/+12
2021-01-19target/arm: do S1_ptw_translate() before address space lookupRémi Denis-Courmont1-3/+6
2021-01-19target/arm: handle VMID change in secure stateRémi Denis-Courmont1-4/+9
2021-01-19target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont1-0/+24
2021-01-19target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont1-43/+84
2021-01-19target/arm: add 64-bit S-EL2 to EL exception tableRémi Denis-Courmont1-5/+5
2021-01-19target/arm: factor MDCR_EL2 common handlingRémi Denis-Courmont1-16/+22
2021-01-19target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont1-13/+18
2021-01-19target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont1-20/+13
2021-01-19target/arm: remove redundant testsRémi Denis-Courmont1-6/+4
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard1-2/+3
2021-01-18target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée1-1/+1
2021-01-12target/arm: ARMv8.4-TTST extensionRémi Denis-Courmont1-2/+13
2021-01-08target/arm: Fix MTE0_ACTIVERichard Henderson1-1/+1
2020-12-19qapi: Use QAPI_LIST_PREPEND() where possibleEric Blake1-5/+1
2020-12-10target/arm: Implement v8.1M PXN extensionPeter Maydell1-1/+6
2020-11-23target/arm: fix stage 2 page-walks in 32-bit emulationRémi Denis-Courmont1-2/+2
2020-11-10target/arm: add spaces around operatorXinhao Zhang1-1/+1