index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
arm
/
helper.c
Age
Commit message (
Expand
)
Author
Files
Lines
2017-11-07
arm: implement cache/shareability attribute bits for PAR registers
Andrew Baumann
1
-14
/
+164
2017-10-12
target/arm: Implement secure function return
Peter Maydell
1
-8
/
+107
2017-10-12
target/arm: Implement BLXNS
Peter Maydell
1
-0
/
+59
2017-10-12
target/arm: Implement SG instruction
Peter Maydell
1
-5
/
+127
2017-10-06
target/arm: Implement security attribute lookups for memory accesses
Peter Maydell
1
-2
/
+180
2017-10-06
target/arm: Add v8M support to exception entry code
Peter Maydell
1
-20
/
+145
2017-10-06
target/arm: Add support for restoring v8M additional state context
Peter Maydell
1
-0
/
+30
2017-10-06
target/arm: Update excret sanity checks for v8M
Peter Maydell
1
-15
/
+58
2017-10-06
target/arm: Don't warn about exception return with PC low bit set for v8M
Peter Maydell
1
-7
/
+15
2017-10-06
target/arm: Warn about restoring to unaligned stack
Peter Maydell
1
-0
/
+7
2017-10-06
target/arm: Check for xPSR mismatch usage faults earlier for v8M
Peter Maydell
1
-3
/
+27
2017-10-06
target/arm: Restore SPSEL to correct CONTROL register on exception return
Peter Maydell
1
-13
/
+27
2017-10-06
target/arm: Restore security state on exception return
Peter Maydell
1
-0
/
+2
2017-10-06
target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode
Peter Maydell
1
-22
/
+43
2017-10-06
target/arm: Don't switch to target stack early in v7M exception return
Peter Maydell
1
-32
/
+98
2017-10-06
arm: Fix SMC reporting to EL2 when QEMU provides PSCI
Jan Kiszka
1
-1
/
+8
2017-09-21
nvic: Support banked exceptions in acknowledge and complete
Peter Maydell
1
-3
/
+5
2017-09-21
nvic: Make set_pending and clear_pending take a secure parameter
Peter Maydell
1
-10
/
+14
2017-09-21
target/arm: Implement MSR/MRS access to NS banked registers
Peter Maydell
1
-0
/
+110
2017-09-14
target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()
Peter Maydell
1
-11
/
+12
2017-09-14
target/arm: Add and use defines for EXCRET constants
Peter Maydell
1
-5
/
+9
2017-09-14
target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()
Peter Maydell
1
-2
/
+2
2017-09-14
target/arm: Get PRECISERR and IBUSERR the right way round
Peter Maydell
1
-4
/
+4
2017-09-14
target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
Peter Maydell
1
-0
/
+2
2017-09-07
target/arm: Implement BXNS, and banked stack pointers
Peter Maydell
1
-0
/
+79
2017-09-07
target/arm: Move regime_is_secure() to target/arm/internals.h
Peter Maydell
1
-26
/
+0
2017-09-07
target/arm: Make CFSR register banked for v8M
Peter Maydell
1
-9
/
+9
2017-09-07
target/arm: Make MMFAR banked for v8M
Peter Maydell
1
-2
/
+2
2017-09-07
target/arm: Make CCR register banked for v8M
Peter Maydell
1
-2
/
+3
2017-09-07
target/arm: Make MPU_CTRL register banked for v8M
Peter Maydell
1
-2
/
+3
2017-09-07
target/arm: Make MPU_RNR register banked for v8M
Peter Maydell
1
-3
/
+3
2017-09-07
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Peter Maydell
1
-5
/
+6
2017-09-07
target/arm: Make VTOR register banked for v8M
Peter Maydell
1
-1
/
+1
2017-09-07
target/arm: Make CONTROL register banked for v8M
Peter Maydell
1
-10
/
+11
2017-09-07
target/arm: Make FAULTMASK register banked for v8M
Peter Maydell
1
-4
/
+16
2017-09-07
target/arm: Make PRIMASK register banked for v8M
Peter Maydell
1
-2
/
+2
2017-09-07
target/arm: Make BASEPRI register banked for v8M
Peter Maydell
1
-4
/
+6
2017-09-07
target/arm: Add MMU indexes for secure v8M
Peter Maydell
1
-1
/
+8
2017-09-07
target/arm: Implement new PMSAv8 behaviour
Peter Maydell
1
-1
/
+110
2017-09-04
target/arm: Create and use new function arm_v7m_is_handler_mode()
Peter Maydell
1
-4
/
+4
2017-09-04
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
Peter Maydell
1
-7
/
+8
2017-09-04
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
Peter Maydell
1
-13
/
+5
2017-09-04
target/arm: Define and use XPSR bit masks
Peter Maydell
1
-7
/
+8
2017-09-04
target/arm: Fix outdated comment about exception exit
Peter Maydell
1
-1
/
+1
2017-09-04
target/arm: Consolidate PMSA handling in get_phys_addr()
Peter Maydell
1
-16
/
+22
2017-09-04
target/arm: Use MMUAccessType enum rather than int
Peter Maydell
1
-15
/
+15
2017-09-01
arm: replace cpu_arm_init() with cpu_generic_init()
Igor Mammedov
1
-5
/
+0
2017-07-31
target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset
Peter Maydell
1
-16
/
+12
2017-07-31
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
Peter Maydell
1
-3
/
+3
2017-07-31
target/arm: Don't allow guest to make System space executable for M profile
Peter Maydell
1
-1
/
+15
[next]