riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-03-10	semihosting: Move include/hw/semihosting/ -> include/semihosting/	Philippe Mathieu-Daudé	1	-2/+2
2021-03-05	target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks	Peter Collingbourne	1	-1/+1
2021-03-05	target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe	Rebecca Cran	1	-0/+37
2021-02-11	target/arm: Correctly initialize MDCR_EL2.HPMN	Daniel Müller	1	-5/+4
2021-02-11	target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate	Rebecca Cran	1	-6/+18
2021-02-11	target/arm: Add support for FEAT_DIT, Data Independent Timing	Rebecca Cran	1	-0/+22
2021-02-11	target/arm: Fix SCR RES1 handling	Mike Nawrocki	1	-2/+14
2021-02-05	target/arm: do not use cc->do_interrupt for KVM directly	Claudio Fontana	1	-0/+4
2021-01-29	target/arm: Replace magic value by MMU_DATA_LOAD definition	Philippe Mathieu-Daudé	1	-1/+1
2021-01-29	target/arm: Conditionalize DBGDIDR	Richard Henderson	1	-6/+15
2021-01-29	target/arm: Implement ID_PFR2	Richard Henderson	1	-2/+2
2021-01-19	target/arm: refactor vae1_tlbmask()	Rémi Denis-Courmont	1	-14/+11
2021-01-19	target/arm: Implement SCR_EL2.EEL2	Rémi Denis-Courmont	1	-3/+16
2021-01-19	target/arm: set HPFAR_EL2.NS on secure stage 2 faults	Rémi Denis-Courmont	1	-0/+6
2021-01-19	target/arm: secure stage 2 translation regime	Rémi Denis-Courmont	1	-24/+54
2021-01-19	target/arm: generalize 2-stage page-walk condition	Rémi Denis-Courmont	1	-7/+6
2021-01-19	target/arm: translate NS bit in page-walks	Rémi Denis-Courmont	1	-0/+12
2021-01-19	target/arm: do S1_ptw_translate() before address space lookup	Rémi Denis-Courmont	1	-3/+6
2021-01-19	target/arm: handle VMID change in secure state	Rémi Denis-Courmont	1	-4/+9
2021-01-19	target/arm: add ARMv8.4-SEL2 system registers	Rémi Denis-Courmont	1	-0/+24
2021-01-19	target/arm: add MMU stage 1 for Secure EL2	Rémi Denis-Courmont	1	-43/+84
2021-01-19	target/arm: add 64-bit S-EL2 to EL exception table	Rémi Denis-Courmont	1	-5/+5
2021-01-19	target/arm: factor MDCR_EL2 common handling	Rémi Denis-Courmont	1	-16/+22
2021-01-19	target/arm: use arm_hcr_el2_eff() where applicable	Rémi Denis-Courmont	1	-13/+18
2021-01-19	target/arm: use arm_is_el2_enabled() where applicable	Rémi Denis-Courmont	1	-20/+13
2021-01-19	target/arm: remove redundant tests	Rémi Denis-Courmont	1	-6/+4
2021-01-18	semihosting: Change common-semi API to be architecture-independent	Keith Packard	1	-2/+3
2021-01-18	target/arm: use official org.gnu.gdb.aarch64.sve layout for registers	Alex Bennée	1	-1/+1
2021-01-12	target/arm: ARMv8.4-TTST extension	Rémi Denis-Courmont	1	-2/+13
2021-01-08	target/arm: Fix MTE0_ACTIVE	Richard Henderson	1	-1/+1
2020-12-19	qapi: Use QAPI_LIST_PREPEND() where possible	Eric Blake	1	-5/+1
2020-12-10	target/arm: Implement v8.1M PXN extension	Peter Maydell	1	-1/+6
2020-11-23	target/arm: fix stage 2 page-walks in 32-bit emulation	Rémi Denis-Courmont	1	-2/+2
2020-11-10	target/arm: add spaces around operator	Xinhao Zhang	1	-1/+1
2020-11-02	target/arm: fix LORID_EL1 access check	Rémi Denis-Courmont	1	-14/+5
2020-11-02	target/arm: fix handling of HCR.FB	Rémi Denis-Courmont	1	-3/+2
2020-10-20	target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11	Richard Henderson	1	-4/+5
2020-10-20	target/arm: Use tlb_flush_page_bits_by_mmuidx*	Richard Henderson	1	-7/+39
2020-10-05	icount: rename functions to be consistent with the module name	Claudio Fontana	1	-2/+2
2020-10-05	cpu-timers, icount: new modules	Claudio Fontana	1	-1/+2
2020-10-01	target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters	Peter Maydell	1	-2/+2
2020-10-01	target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check	Peter Maydell	1	-2/+3
2020-09-14	target/arm: Count PMU events when MDCR.SPME is set	Aaron Lindsay	1	-1/+1
2020-08-28	target/arm: Clarify HCR_EL2 ARMCPRegInfo type	Philippe Mathieu-Daudé	1	-1/+0
2020-08-24	target/arm: Convert A32 coprocessor insns to decodetree	Peter Maydell	1	-0/+29
2020-08-05	target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64	Peter Maydell	1	-1/+91
2020-07-27	target/arm: Always pass cacheattr in S1_ptw_translate	Richard Henderson	1	-13/+6
2020-07-13	target/arm: Don't do raw writes for PMINTENCLR	Aaron Lindsay	1	-2/+2
2020-06-26	target/arm: Cache the Tagged bit for a page in MemTxAttrs	Richard Henderson	1	-3/+45
2020-06-26	target/arm: Always pass cacheattr to get_phys_addr	Richard Henderson	1	-30/+30