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path: root/target/arm/helper-a64.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-22target/arm: Change CPUArchState.aarch64 to boolRichard Henderson1-2/+2
2022-02-08arm: force flag recalculation when messing with DAIFAlex Bennée1-0/+2
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot1-4/+4
2021-10-13target/arm: Use cpu_*_mmu instead of helper_*_mmuRichard Henderson1-44/+8
2021-10-13accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.hRichard Henderson1-1/+0
2021-10-13target/arm: Use MO_128 for 16 byte atomicsRichard Henderson1-4/+4
2021-10-05tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson1-8/+8
2021-09-13target/arm: Take an exception if PSTATE.IL is setPeter Maydell1-0/+1
2021-07-21tcg: Rename helper_atomic_*_mmu and provide for user-onlyRichard Henderson1-4/+4
2021-07-02target/arm: Check NaN mode before silencing NaNJoe Komlodi1-3/+9
2021-04-30target/arm: Add wrapper macros for accessing tbflagsRichard Henderson1-1/+1
2021-03-05target/arm: Speed up aarch64 TBL/TBXRichard Henderson1-32/+0
2021-02-16exec: Use cpu_untagged_addr in g2h; split out g2h_untaggedRichard Henderson1-2/+2
2021-02-11target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstateRebecca Cran1-4/+23
2021-01-19target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont1-7/+1
2020-11-15arm tcg cpus: Fix Lesser GPL version numberChetan Pant1-1/+1
2020-09-01target/arm: Remove local definitions of float constantsPeter Maydell1-11/+0
2020-06-26target/arm: Simplify DC_ZVARichard Henderson1-70/+26
2020-03-05target/arm: Move helper_dc_zva to helper-a64.cRichard Henderson1-0/+91
2020-03-05target/arm: Apply TBI to ESR_ELx in helper_exception_returnRichard Henderson1-1/+22
2020-02-13target/arm: Introduce aarch64_pstate_valid_maskRichard Henderson1-0/+1
2020-02-13target/arm: Use aarch32_cpsr_valid_mask in helper_exception_returnRichard Henderson1-2/+3
2020-02-07target/arm: Update arm_sctlr for VHERichard Henderson1-1/+1
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2019-10-24target/arm: Rebuild hflags at EL changesRichard Henderson1-0/+3
2019-08-16Clean up inclusion of sysemu/sysemu.hMarkus Armbruster1-1/+0
2019-08-16Include qemu/main-loop.h lessMarkus Armbruster1-0/+1
2019-07-14tcg: Introduce set/clear_helper_retaddrRichard Henderson1-4/+4
2019-06-10target/arm: Use env_cpu, env_archcpuRichard Henderson1-2/+2
2019-03-05target/arm: Split helper_msr_i_pstate into 3Richard Henderson1-0/+30
2019-02-15target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_beCatherine Ho1-2/+2
2019-01-21target/arm: Add new_pc argument to helper_exception_returnRichard Henderson1-5/+5
2019-01-21target/arm: Move helper_exception_return to helper-a64.cRichard Henderson1-0/+155
2018-10-18target/arm: Check HAVE_CMPXCHG128 at translate timeRichard Henderson1-12/+4
2018-10-18target/arm: Convert to HAVE_CMPXCHG128Richard Henderson1-127/+134
2018-05-31tcg: Fix helper function vs host abi for float16Richard Henderson1-17/+18
2018-05-31target/arm: Honour FPCR.FZ in FRECPXPeter Maydell1-0/+6
2018-05-17target/arm: Remove floatX_maybe_silence_nan from conversionsRichard Henderson1-1/+0
2018-05-17target/arm: Use floatX_silence_nan when we have already checked for SNaNRichard Henderson1-3/+3
2018-05-15target/arm: Implement FCMP for fp16Alex Bennée1-0/+10
2018-05-10target/arm: Implement CAS and CASPRichard Henderson1-0/+43
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée1-0/+13
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée1-0/+29
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée1-0/+32
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée1-0/+22
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée1-1/+45
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée1-0/+34
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée1-0/+24
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée1-0/+49
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée1-0/+4
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