Age | Commit message (Expand) | Author | Files | Lines |
2022-04-22 | target/arm: Change CPUArchState.aarch64 to bool | Richard Henderson | 1 | -2/+2 |
2022-02-08 | arm: force flag recalculation when messing with DAIF | Alex Bennée | 1 | -0/+2 |
2022-01-08 | exec/memop: Adding signedness to quad definitions | Frédéric Pétrot | 1 | -4/+4 |
2021-10-13 | target/arm: Use cpu_*_mmu instead of helper_*_mmu | Richard Henderson | 1 | -44/+8 |
2021-10-13 | accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h | Richard Henderson | 1 | -1/+0 |
2021-10-13 | target/arm: Use MO_128 for 16 byte atomics | Richard Henderson | 1 | -4/+4 |
2021-10-05 | tcg: Rename TCGMemOpIdx to MemOpIdx | Richard Henderson | 1 | -8/+8 |
2021-09-13 | target/arm: Take an exception if PSTATE.IL is set | Peter Maydell | 1 | -0/+1 |
2021-07-21 | tcg: Rename helper_atomic_*_mmu and provide for user-only | Richard Henderson | 1 | -4/+4 |
2021-07-02 | target/arm: Check NaN mode before silencing NaN | Joe Komlodi | 1 | -3/+9 |
2021-04-30 | target/arm: Add wrapper macros for accessing tbflags | Richard Henderson | 1 | -1/+1 |
2021-03-05 | target/arm: Speed up aarch64 TBL/TBX | Richard Henderson | 1 | -32/+0 |
2021-02-16 | exec: Use cpu_untagged_addr in g2h; split out g2h_untagged | Richard Henderson | 1 | -2/+2 |
2021-02-11 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate | Rebecca Cran | 1 | -4/+23 |
2021-01-19 | target/arm: use arm_is_el2_enabled() where applicable | Rémi Denis-Courmont | 1 | -7/+1 |
2020-11-15 | arm tcg cpus: Fix Lesser GPL version number | Chetan Pant | 1 | -1/+1 |
2020-09-01 | target/arm: Remove local definitions of float constants | Peter Maydell | 1 | -11/+0 |
2020-06-26 | target/arm: Simplify DC_ZVA | Richard Henderson | 1 | -70/+26 |
2020-03-05 | target/arm: Move helper_dc_zva to helper-a64.c | Richard Henderson | 1 | -0/+91 |
2020-03-05 | target/arm: Apply TBI to ESR_ELx in helper_exception_return | Richard Henderson | 1 | -1/+22 |
2020-02-13 | target/arm: Introduce aarch64_pstate_valid_mask | Richard Henderson | 1 | -0/+1 |
2020-02-13 | target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return | Richard Henderson | 1 | -2/+3 |
2020-02-07 | target/arm: Update arm_sctlr for VHE | Richard Henderson | 1 | -1/+1 |
2020-01-15 | tcg: Search includes from the project root source directory | Philippe Mathieu-Daudé | 1 | -1/+1 |
2019-10-24 | target/arm: Rebuild hflags at EL changes | Richard Henderson | 1 | -0/+3 |
2019-08-16 | Clean up inclusion of sysemu/sysemu.h | Markus Armbruster | 1 | -1/+0 |
2019-08-16 | Include qemu/main-loop.h less | Markus Armbruster | 1 | -0/+1 |
2019-07-14 | tcg: Introduce set/clear_helper_retaddr | Richard Henderson | 1 | -4/+4 |
2019-06-10 | target/arm: Use env_cpu, env_archcpu | Richard Henderson | 1 | -2/+2 |
2019-03-05 | target/arm: Split helper_msr_i_pstate into 3 | Richard Henderson | 1 | -0/+30 |
2019-02-15 | target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be | Catherine Ho | 1 | -2/+2 |
2019-01-21 | target/arm: Add new_pc argument to helper_exception_return | Richard Henderson | 1 | -5/+5 |
2019-01-21 | target/arm: Move helper_exception_return to helper-a64.c | Richard Henderson | 1 | -0/+155 |
2018-10-18 | target/arm: Check HAVE_CMPXCHG128 at translate time | Richard Henderson | 1 | -12/+4 |
2018-10-18 | target/arm: Convert to HAVE_CMPXCHG128 | Richard Henderson | 1 | -127/+134 |
2018-05-31 | tcg: Fix helper function vs host abi for float16 | Richard Henderson | 1 | -17/+18 |
2018-05-31 | target/arm: Honour FPCR.FZ in FRECPX | Peter Maydell | 1 | -0/+6 |
2018-05-17 | target/arm: Remove floatX_maybe_silence_nan from conversions | Richard Henderson | 1 | -1/+0 |
2018-05-17 | target/arm: Use floatX_silence_nan when we have already checked for SNaN | Richard Henderson | 1 | -3/+3 |
2018-05-15 | target/arm: Implement FCMP for fp16 | Alex Bennée | 1 | -0/+10 |
2018-05-10 | target/arm: Implement CAS and CASP | Richard Henderson | 1 | -0/+43 |
2018-03-01 | arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 | Alex Bennée | 1 | -0/+13 |
2018-03-01 | arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 | Alex Bennée | 1 | -0/+29 |
2018-03-01 | arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 | Alex Bennée | 1 | -0/+32 |
2018-03-01 | arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 | Alex Bennée | 1 | -0/+22 |
2018-03-01 | arm/translate-a64: add FP16 x2 ops for simd_indexed | Alex Bennée | 1 | -1/+45 |
2018-03-01 | arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 | Alex Bennée | 1 | -0/+34 |
2018-03-01 | arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 | Alex Bennée | 1 | -0/+24 |
2018-03-01 | arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 | Alex Bennée | 1 | -0/+49 |
2018-03-01 | arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 | Alex Bennée | 1 | -0/+4 |