riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-05-19	target/arm: Make number of counters in PMCR follow the CPU	Peter Maydell	1	-0/+6
2022-05-09	target/arm: Enable FEAT_CSV3 for -cpu max	Richard Henderson	1	-0/+1
2022-05-09	target/arm: Enable FEAT_CSV2 for -cpu max	Richard Henderson	1	-0/+1
2022-05-09	target/arm: Enable FEAT_RAS for -cpu max	Richard Henderson	1	-0/+1
2022-05-09	target/arm: Enable FEAT_Debugv8p4 for -cpu max	Richard Henderson	1	-2/+2
2022-05-09	target/arm: Enable FEAT_Debugv8p2 for -cpu max	Richard Henderson	1	-0/+2
2022-05-09	target/arm: Annotate arm_max_initfn with FEAT identifiers	Richard Henderson	1	-24/+24
2022-05-09	target/arm: Split out aa32_max_features	Richard Henderson	1	-53/+61
2022-05-09	target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max	Richard Henderson	1	-0/+4
2022-05-09	target/arm: Update qemu-system-arm -cpu max to cortex-a57	Richard Henderson	1	-60/+93
2022-05-09	target/arm: Move cortex impdef sysregs to cpu_tcg.c	Richard Henderson	1	-0/+59
2022-05-05	target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h	Richard Henderson	1	-4/+0
2022-05-05	target/arm: Split out cpregs.h	Richard Henderson	1	-0/+1
2021-11-02	target/arm: Implement arm_cpu_record_sigbus	Richard Henderson	1	-0/+1
2021-11-02	target/arm: Implement arm_cpu_record_sigsegv	Richard Henderson	1	-2/+4
2021-09-14	target/arm: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé	1	-3/+3
2021-09-01	target/arm: Enable MVE in Cortex-M55	Peter Maydell	1	-5/+2
2021-07-21	target/arm: Implement debug_check_breakpoint	Richard Henderson	1	-0/+1
2021-06-03	target/arm: Enable BFloat16 extensions	Richard Henderson	1	-0/+1
2021-05-26	hw/core: Constify TCGCPUOps	Richard Henderson	1	-1/+1
2021-05-25	target/arm: Enable SVE2 and related extensions	Richard Henderson	1	-0/+1
2021-04-06	Revert "target/arm: Make number of counters in PMCR follow the CPU"	Peter Maydell	1	-5/+0
2021-03-30	target/arm: Make number of counters in PMCR follow the CPU	Peter Maydell	1	-0/+5
2021-03-08	target/arm: Restrict v7A TCG cpus to TCG accel	Philippe Mathieu-Daudé	1	-0/+318
2021-03-05	target/arm: Restrict v8M IDAU to TCG	Philippe Mathieu-Daudé	1	-0/+8
2021-02-05	cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass	Claudio Fontana	1	-5/+23
2021-02-05	cpu: move cc->do_interrupt to tcg_ops	Claudio Fontana	1	-5/+4
2021-02-05	cpu: Move cpu_exec_* to tcg_ops	Eduardo Habkost	1	-1/+6
2021-01-08	target/arm: Implement Cortex-M55 model	Peter Maydell	1	-0/+42
2020-10-01	target/arm: Add ID register values for Cortex-M0	Peter Maydell	1	-0/+24
2020-10-01	target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters	Peter Maydell	1	-18/+18
2020-05-14	target/arm: Use correct GDB XML for M-profile cores	Peter Maydell	1	-0/+1
2020-05-11	target/arm: Restrict TCG cpus to TCG accel	Philippe Mathieu-Daudé	1	-0/+664