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target
/
arm
/
cpu.h
Age
Commit message (
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Author
Files
Lines
2018-03-02
target/arm: Add ARM_FEATURE_V8_FCMA
Richard Henderson
1
-0
/
+1
2018-03-02
target/arm: Add ARM_FEATURE_V8_RDM
Richard Henderson
1
-0
/
+1
2018-03-02
target/arm: Define init-svtor property for the reset secure VTOR value
Peter Maydell
1
-0
/
+3
2018-03-02
target/arm: Define an IDAU interface
Peter Maydell
1
-0
/
+3
2018-03-01
target/arm/cpu.h: add additional float_status flags
Alex Bennée
1
-7
/
+25
2018-03-01
target/arm/cpu.h: update comment for half-precision values
Alex Bennée
1
-0
/
+1
2018-03-01
target/arm/cpu64: introduce ARM_V8_FP16 feature bit
Alex Bennée
1
-0
/
+1
2018-02-21
target/*/cpu.h: remove softfloat.h
Alex Bennée
1
-2
/
+0
2018-02-15
target/arm: Implement v8M MSPLIM and PSPLIM registers
Peter Maydell
1
-0
/
+2
2018-02-15
hw/intc/armv7m_nvic: Implement SCR
Peter Maydell
1
-0
/
+7
2018-02-15
hw/intc/armv7m_nvic: Implement cache ID registers
Peter Maydell
1
-0
/
+26
2018-02-15
target/arm: Enforce access to ZCR_EL at translation
Richard Henderson
1
-1
/
+2
2018-02-15
target/arm: Enforce FP access to FPCR/FPSR
Richard Henderson
1
-17
/
+18
2018-02-09
target/arm: Add SVE state to TB->FLAGS
Richard Henderson
1
-0
/
+8
2018-02-09
target/arm: Add ZCR_ELx
Richard Henderson
1
-0
/
+5
2018-02-09
target/arm: Add predicate registers for SVE
Richard Henderson
1
-0
/
+12
2018-02-09
target/arm: Expand vector registers for SVE
Richard Henderson
1
-19
/
+40
2018-02-09
target/arm: implement SM4 instructions
Ard Biesheuvel
1
-0
/
+1
2018-02-09
target/arm: implement SM3 instructions
Ard Biesheuvel
1
-0
/
+1
2018-02-09
target/arm: implement SHA-3 instructions
Ard Biesheuvel
1
-0
/
+1
2018-02-09
target/arm: implement SHA-512 instructions
Ard Biesheuvel
1
-0
/
+1
2018-02-09
target/arm: Split "get pending exception info" from "acknowledge it"
Peter Maydell
1
-3
/
+16
2018-02-09
target/arm: Add armv7m_nvic_set_pending_derived()
Peter Maydell
1
-0
/
+13
2018-02-08
target/arm: Align vector registers
Richard Henderson
1
-1
/
+1
2018-01-25
target/arm: Move cpu_get_tb_cpu_state out of line
Richard Henderson
1
-125
/
+2
2018-01-25
target/arm: Add ARM_FEATURE_SVE
Richard Henderson
1
-0
/
+1
2018-01-25
target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
Richard Henderson
1
-0
/
+27
2018-01-25
target/arm: Change the type of vfp.regs
Richard Henderson
1
-1
/
+1
2017-12-13
target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()
Peter Maydell
1
-5
/
+16
2017-12-13
target/arm: Split M profile MNegPri mmu index into user and priv
Peter Maydell
1
-21
/
+33
2017-10-06
target/arm: Factor out "get mmuidx for specified security state"
Peter Maydell
1
-11
/
+21
2017-10-06
target/arm: Fix calculation of secure mm_idx values
Peter Maydell
1
-5
/
+7
2017-10-06
nvic: Implement Security Attribution Unit registers
Peter Maydell
1
-0
/
+10
2017-10-06
target/arm: Add new-in-v8M SFSR and SFAR
Peter Maydell
1
-0
/
+12
2017-10-06
target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode
Peter Maydell
1
-1
/
+7
2017-09-21
nvic: Support banked exceptions in acknowledge and complete
Peter Maydell
1
-2
/
+13
2017-09-21
target/arm: Handle banking in negative-execution-priority check in cpu_mmu_in...
Peter Maydell
1
-5
/
+16
2017-09-21
nvic: Make set_pending and clear_pending take a secure parameter
Peter Maydell
1
-1
/
+13
2017-09-21
nvic: Implement AIRCR changes for v8M
Peter Maydell
1
-0
/
+12
2017-09-19
arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly
Igor Mammedov
1
-0
/
+3
2017-09-14
target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2
Peter Maydell
1
-16
/
+19
2017-09-07
target/arm: Add Jazelle feature
Portia Stephens
1
-0
/
+1
2017-09-07
target/arm: Implement BXNS, and banked stack pointers
Peter Maydell
1
-0
/
+13
2017-09-07
target/arm: Make CFSR register banked for v8M
Peter Maydell
1
-1
/
+6
2017-09-07
target/arm: Make MMFAR banked for v8M
Peter Maydell
1
-1
/
+1
2017-09-07
target/arm: Make CCR register banked for v8M
Peter Maydell
1
-1
/
+1
2017-09-07
target/arm: Make MPU_CTRL register banked for v8M
Peter Maydell
1
-1
/
+1
2017-09-07
target/arm: Make MPU_RNR register banked for v8M
Peter Maydell
1
-1
/
+1
2017-09-07
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Peter Maydell
1
-2
/
+2
2017-09-07
target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
Peter Maydell
1
-2
/
+2
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