| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-01-27 | armv7m: Report no-coprocessor faults correctly | Peter Maydell | 1 | -0/+1 |
| 2017-01-27 | armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR | Peter Maydell | 1 | -0/+54 |
| 2017-01-27 | target/arm: Drop IS_M() macro | Peter Maydell | 1 | -6/+0 |
| 2017-01-27 | armv7m: Fix reads of CONTROL register bit 1 | Michael Davidsaver | 1 | -1/+0 |
| 2017-01-20 | target-arm: Enable EL2 feature bit on A53 and A57 | Peter Maydell | 1 | -0/+2 |
| 2017-01-20 | target-arm: Add ARMCPU fields for GIC CPU i/f config | Peter Maydell | 1 | -0/+5 |
| 2017-01-20 | target-arm: Expose output GPIO line for VCPU maintenance interrupt | Peter Maydell | 1 | -0/+2 |
| 2017-01-13 | qom/cpu: move tlb_flush to cpu_common_reset | Alex Bennée | 1 | -1/+4 |
| 2016-12-27 | target-arm: Add VBAR support to ARM1176 CPUs | Cédric Le Goater | 1 | -0/+1 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+2466 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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