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target-xtensa
Age
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Author
Files
Lines
2012-04-15
target-xtensa: add license to core-dc232b.c
Max Filippov
1
-0
/
+27
2012-04-15
target-xtensa: add dc233c core
Max Filippov
3
-0
/
+674
2012-04-14
target-xtensa: fix tb invalidation for IBREAK and LOOP
Max Filippov
2
-11
/
+20
2012-04-14
Use uintptr_t for various op related functions
Blue Swirl
1
-5
/
+4
2012-04-14
target-xtensa: Start QOM'ifying CPU init
Andreas Färber
2
-1
/
+9
2012-04-14
target-xtensa: QOM'ify CPU reset
Andreas Färber
3
-14
/
+14
2012-04-14
target-xtensa: QOM'ify CPU
Andreas Färber
4
-1
/
+153
2012-04-14
target-xtensa: Move helpers.h to helper.h
Lluís Vilanova
3
-4
/
+4
2012-03-14
Rename CPUState -> CPUArchState
Andreas Färber
1
-1
/
+1
2012-03-14
target-xtensa: Don't overuse CPUState
Andreas Färber
4
-68
/
+68
2012-03-14
Rename cpu_reset() to cpu_state_reset()
Andreas Färber
1
-1
/
+1
2012-03-03
Merge branch 'upstream' of git://qemu.weilnetz.de/qemu
Blue Swirl
3
-3
/
+0
2012-02-28
target-xtensa: Clean includes
Stefan Weil
3
-3
/
+0
2012-02-20
target-xtensa: add DEBUG_SECTION to overlay tool
Max Filippov
3
-0
/
+7
2012-02-20
target-xtensa: add DBREAK data breakpoints
Max Filippov
5
-0
/
+147
2012-02-18
target-xtensa: add ICOUNT SR and debug exception
Max Filippov
2
-1
/
+54
2012-02-18
target-xtensa: implement instruction breakpoints
Max Filippov
5
-3
/
+119
2012-02-18
target-xtensa: add DEBUGCAUSE SR and configuration
Max Filippov
2
-0
/
+21
2012-02-18
target-xtensa: fetch 3rd opcode byte only when needed
Max Filippov
1
-1
/
+2
2012-02-18
target-xtensa: implement info tlb monitor command
Max Filippov
2
-0
/
+68
2012-02-18
target-xtensa: define TLB_TEMPLATE for MMU-less cores
Max Filippov
1
-2
/
+16
2011-11-26
target-xtensa: fix MMUv3 initialization
Max Filippov
2
-2
/
+2
2011-11-02
target-xtensa: raise an exception for invalid and reserved opcodes
Max Filippov
1
-1
/
+6
2011-11-02
target-xtensa: handle cache options in the overlay tool
Max Filippov
1
-0
/
+6
2011-11-02
target-xtensa: mask out undefined bits of WINDOWSTART SR
Max Filippov
1
-1
/
+1
2011-10-16
target-xtensa: add fsf core
Max Filippov
2
-0
/
+383
2011-10-16
target-xtensa: add dc232b core
Max Filippov
3
-0
/
+712
2011-10-16
target-xtensa: extract core configuration from overlay
Max Filippov
3
-13
/
+554
2011-10-16
target-xtensa: implement external interrupt mapping
Max Filippov
1
-0
/
+3
2011-10-16
target-xtensa: remove hand-written xtensa cores implementations
Max Filippov
3
-860
/
+2
2011-10-16
target-xtensa: increase xtensa options accuracy
Max Filippov
2
-8
/
+12
2011-10-15
target-xtensa: implement MAC16 option
Max Filippov
2
-1
/
+137
2011-10-15
target-xtensa: fix guest hang on masked CCOMPARE interrupt
Max Filippov
2
-15
/
+4
2011-10-01
softmmu_header: pass CPUState to tlb_fill
Blue Swirl
1
-2
/
+3
2011-09-10
target-xtensa: add dc232b core and board
Max Filippov
2
-0
/
+429
2011-09-10
target-xtensa: implement boolean option
Max Filippov
2
-24
/
+86
2011-09-10
target-xtensa: implement memory protection options
Max Filippov
5
-13
/
+782
2011-09-10
target-xtensa: add gdb support
Max Filippov
3
-0
/
+400
2011-09-10
target-xtensa: implement relocatable vectors
Max Filippov
3
-2
/
+19
2011-09-10
target-xtensa: implement CPENABLE and PRID SRs
Max Filippov
2
-0
/
+9
2011-09-10
target-xtensa: implement accurate window check
Max Filippov
1
-0
/
+110
2011-09-10
target-xtensa: implement interrupt option
Max Filippov
5
-12
/
+335
2011-09-10
target-xtensa: implement SIMCALL
Max Filippov
2
-1
/
+9
2011-09-10
target-xtensa: implement unaligned exception option
Max Filippov
3
-4
/
+73
2011-09-10
target-xtensa: implement extended L32R
Max Filippov
3
-4
/
+40
2011-09-10
target-xtensa: implement loop option
Max Filippov
4
-9
/
+93
2011-09-10
target-xtensa: implement windowed registers
Max Filippov
5
-9
/
+345
2011-09-10
target-xtensa: implement RST2 group (32 bit mul/div/rem)
Max Filippov
1
-1
/
+76
2011-09-10
target-xtensa: implement exceptions
Max Filippov
5
-6
/
+236
2011-09-10
target-xtensa: add PS register and access control
Max Filippov
3
-6
/
+77
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