index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-xtensa
Age
Commit message (
Expand
)
Author
Files
Lines
2012-06-25
target-xtensa: drop usage of prev_debug_excp_handler
Igor Mammedov
1
-7
/
+1
2012-06-10
target-xtensa: switch to AREG0-free mode
Max Filippov
4
-154
/
+151
2012-06-10
target-xtensa: add attributes to helper functions
Max Filippov
1
-8
/
+8
2012-06-10
target-xtensa: remove unnecessary include of dyngen-exec.h
Peter Portante
1
-1
/
+0
2012-06-09
target-xtensa: fix CCOUNT for conditional branches
Max Filippov
1
-0
/
+2
2012-06-09
target-xtensa: control page table lookup explicitly
Max Filippov
1
-5
/
+5
2012-06-09
target-xtensa: update autorefill TLB entries conditionally
Max Filippov
3
-27
/
+35
2012-06-09
target-xtensa: extract TLB entry setting method
Max Filippov
2
-4
/
+14
2012-06-09
target-xtensa: update EXCVADDR in case of page table lookup
Max Filippov
1
-0
/
+1
2012-06-09
target-xtensa: flush TLB page for new MMU mapping
Max Filippov
1
-0
/
+1
2012-06-07
build: move other target-*/ objects to nested Makefile.objs
Paolo Bonzini
1
-1
/
+2
2012-06-07
build: move libobj-y variable to nested Makefile.objs
Paolo Bonzini
1
-0
/
+3
2012-06-07
build: move obj-TARGET-y variables to nested Makefile.objs
Paolo Bonzini
2
-0
/
+228
2012-06-04
Kill off cpu_state_reset()
Andreas Färber
1
-5
/
+0
2012-06-04
target-xtensa: Let cpu_xtensa_init() return XtensaCPU
Andreas Färber
3
-6
/
+16
2012-04-21
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
Max Filippov
1
-1
/
+1
2012-04-15
target-xtensa: add license to core-fsf.c
Max Filippov
1
-0
/
+27
2012-04-15
target-xtensa: add license to core-dc232b.c
Max Filippov
1
-0
/
+27
2012-04-15
target-xtensa: add dc233c core
Max Filippov
3
-0
/
+674
2012-04-14
target-xtensa: fix tb invalidation for IBREAK and LOOP
Max Filippov
2
-11
/
+20
2012-04-14
Use uintptr_t for various op related functions
Blue Swirl
1
-5
/
+4
2012-04-14
target-xtensa: Start QOM'ifying CPU init
Andreas Färber
2
-1
/
+9
2012-04-14
target-xtensa: QOM'ify CPU reset
Andreas Färber
3
-14
/
+14
2012-04-14
target-xtensa: QOM'ify CPU
Andreas Färber
4
-1
/
+153
2012-04-14
target-xtensa: Move helpers.h to helper.h
Lluís Vilanova
3
-4
/
+4
2012-03-14
Rename CPUState -> CPUArchState
Andreas Färber
1
-1
/
+1
2012-03-14
target-xtensa: Don't overuse CPUState
Andreas Färber
4
-68
/
+68
2012-03-14
Rename cpu_reset() to cpu_state_reset()
Andreas Färber
1
-1
/
+1
2012-03-03
Merge branch 'upstream' of git://qemu.weilnetz.de/qemu
Blue Swirl
3
-3
/
+0
2012-02-28
target-xtensa: Clean includes
Stefan Weil
3
-3
/
+0
2012-02-20
target-xtensa: add DEBUG_SECTION to overlay tool
Max Filippov
3
-0
/
+7
2012-02-20
target-xtensa: add DBREAK data breakpoints
Max Filippov
5
-0
/
+147
2012-02-18
target-xtensa: add ICOUNT SR and debug exception
Max Filippov
2
-1
/
+54
2012-02-18
target-xtensa: implement instruction breakpoints
Max Filippov
5
-3
/
+119
2012-02-18
target-xtensa: add DEBUGCAUSE SR and configuration
Max Filippov
2
-0
/
+21
2012-02-18
target-xtensa: fetch 3rd opcode byte only when needed
Max Filippov
1
-1
/
+2
2012-02-18
target-xtensa: implement info tlb monitor command
Max Filippov
2
-0
/
+68
2012-02-18
target-xtensa: define TLB_TEMPLATE for MMU-less cores
Max Filippov
1
-2
/
+16
2011-11-26
target-xtensa: fix MMUv3 initialization
Max Filippov
2
-2
/
+2
2011-11-02
target-xtensa: raise an exception for invalid and reserved opcodes
Max Filippov
1
-1
/
+6
2011-11-02
target-xtensa: handle cache options in the overlay tool
Max Filippov
1
-0
/
+6
2011-11-02
target-xtensa: mask out undefined bits of WINDOWSTART SR
Max Filippov
1
-1
/
+1
2011-10-16
target-xtensa: add fsf core
Max Filippov
2
-0
/
+383
2011-10-16
target-xtensa: add dc232b core
Max Filippov
3
-0
/
+712
2011-10-16
target-xtensa: extract core configuration from overlay
Max Filippov
3
-13
/
+554
2011-10-16
target-xtensa: implement external interrupt mapping
Max Filippov
1
-0
/
+3
2011-10-16
target-xtensa: remove hand-written xtensa cores implementations
Max Filippov
3
-860
/
+2
2011-10-16
target-xtensa: increase xtensa options accuracy
Max Filippov
2
-8
/
+12
2011-10-15
target-xtensa: implement MAC16 option
Max Filippov
2
-1
/
+137
2011-10-15
target-xtensa: fix guest hang on masked CCOMPARE interrupt
Max Filippov
2
-15
/
+4
[prev]
[next]