Age | Commit message (Expand) | Author | Files | Lines |
2011-11-26 | target-xtensa: fix MMUv3 initialization | Max Filippov | 2 | -2/+2 |
2011-11-02 | target-xtensa: raise an exception for invalid and reserved opcodes | Max Filippov | 1 | -1/+6 |
2011-11-02 | target-xtensa: handle cache options in the overlay tool | Max Filippov | 1 | -0/+6 |
2011-11-02 | target-xtensa: mask out undefined bits of WINDOWSTART SR | Max Filippov | 1 | -1/+1 |
2011-10-16 | target-xtensa: add fsf core | Max Filippov | 2 | -0/+383 |
2011-10-16 | target-xtensa: add dc232b core | Max Filippov | 3 | -0/+712 |
2011-10-16 | target-xtensa: extract core configuration from overlay | Max Filippov | 3 | -13/+554 |
2011-10-16 | target-xtensa: implement external interrupt mapping | Max Filippov | 1 | -0/+3 |
2011-10-16 | target-xtensa: remove hand-written xtensa cores implementations | Max Filippov | 3 | -860/+2 |
2011-10-16 | target-xtensa: increase xtensa options accuracy | Max Filippov | 2 | -8/+12 |
2011-10-15 | target-xtensa: implement MAC16 option | Max Filippov | 2 | -1/+137 |
2011-10-15 | target-xtensa: fix guest hang on masked CCOMPARE interrupt | Max Filippov | 2 | -15/+4 |
2011-10-01 | softmmu_header: pass CPUState to tlb_fill | Blue Swirl | 1 | -2/+3 |
2011-09-10 | target-xtensa: add dc232b core and board | Max Filippov | 2 | -0/+429 |
2011-09-10 | target-xtensa: implement boolean option | Max Filippov | 2 | -24/+86 |
2011-09-10 | target-xtensa: implement memory protection options | Max Filippov | 5 | -13/+782 |
2011-09-10 | target-xtensa: add gdb support | Max Filippov | 3 | -0/+400 |
2011-09-10 | target-xtensa: implement relocatable vectors | Max Filippov | 3 | -2/+19 |
2011-09-10 | target-xtensa: implement CPENABLE and PRID SRs | Max Filippov | 2 | -0/+9 |
2011-09-10 | target-xtensa: implement accurate window check | Max Filippov | 1 | -0/+110 |
2011-09-10 | target-xtensa: implement interrupt option | Max Filippov | 5 | -12/+335 |
2011-09-10 | target-xtensa: implement SIMCALL | Max Filippov | 2 | -1/+9 |
2011-09-10 | target-xtensa: implement unaligned exception option | Max Filippov | 3 | -4/+73 |
2011-09-10 | target-xtensa: implement extended L32R | Max Filippov | 3 | -4/+40 |
2011-09-10 | target-xtensa: implement loop option | Max Filippov | 4 | -9/+93 |
2011-09-10 | target-xtensa: implement windowed registers | Max Filippov | 5 | -9/+345 |
2011-09-10 | target-xtensa: implement RST2 group (32 bit mul/div/rem) | Max Filippov | 1 | -1/+76 |
2011-09-10 | target-xtensa: implement exceptions | Max Filippov | 5 | -6/+236 |
2011-09-10 | target-xtensa: add PS register and access control | Max Filippov | 3 | -6/+77 |
2011-09-10 | target-xtensa: implement CACHE group | Max Filippov | 1 | -1/+94 |
2011-09-10 | target-xtensa: implement SYNC group | Max Filippov | 1 | -1/+30 |
2011-09-10 | target-xtensa: mark reserved and TBD opcodes | Max Filippov | 1 | -1/+109 |
2011-09-10 | target-xtensa: implement LSAI group | Max Filippov | 2 | -0/+90 |
2011-09-10 | target-xtensa: implement shifts (ST1 and RST1 groups) | Max Filippov | 4 | -0/+262 |
2011-09-10 | target-xtensa: implement RST3 group | Max Filippov | 1 | -0/+161 |
2011-09-10 | target-xtensa: add special and user registers | Max Filippov | 2 | -2/+54 |
2011-09-10 | target-xtensa: implement JX/RET0/CALLX | Max Filippov | 1 | -0/+43 |
2011-09-10 | target-xtensa: implement conditional jumps | Max Filippov | 1 | -0/+164 |
2011-09-10 | target-xtensa: implement RT0 group | Max Filippov | 1 | -0/+19 |
2011-09-10 | target-xtensa: implement narrow instructions | Max Filippov | 1 | -0/+54 |
2011-09-10 | target-xtensa: implement disas_xtensa_insn | Max Filippov | 5 | -2/+556 |
2011-09-10 | target-xtensa: add target stubs | Max Filippov | 5 | -0/+326 |