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AgeCommit message (Expand)AuthorFilesLines
2012-06-04target-xtensa: Let cpu_xtensa_init() return XtensaCPUAndreas Färber3-6/+16
2012-04-21target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov1-1/+1
2012-04-15target-xtensa: add license to core-fsf.cMax Filippov1-0/+27
2012-04-15target-xtensa: add license to core-dc232b.cMax Filippov1-0/+27
2012-04-15target-xtensa: add dc233c coreMax Filippov3-0/+674
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov2-11/+20
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-5/+4
2012-04-14target-xtensa: Start QOM'ifying CPU initAndreas Färber2-1/+9
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber3-14/+14
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber4-1/+153
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova3-4/+4
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber4-68/+68
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber1-1/+1
2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl3-3/+0
2012-02-28target-xtensa: Clean includesStefan Weil3-3/+0
2012-02-20target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov3-0/+7
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov5-0/+147
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov2-1/+54
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov5-3/+119
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov2-0/+21
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov1-1/+2
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov2-0/+68
2012-02-18target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov1-2/+16
2011-11-26target-xtensa: fix MMUv3 initializationMax Filippov2-2/+2
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov1-1/+6
2011-11-02target-xtensa: handle cache options in the overlay toolMax Filippov1-0/+6
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov1-1/+1
2011-10-16target-xtensa: add fsf coreMax Filippov2-0/+383
2011-10-16target-xtensa: add dc232b coreMax Filippov3-0/+712
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov3-13/+554
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov1-0/+3
2011-10-16target-xtensa: remove hand-written xtensa cores implementationsMax Filippov3-860/+2
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov2-8/+12
2011-10-15target-xtensa: implement MAC16 optionMax Filippov2-1/+137
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov2-15/+4
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl1-2/+3
2011-09-10target-xtensa: add dc232b core and boardMax Filippov2-0/+429
2011-09-10target-xtensa: implement boolean optionMax Filippov2-24/+86
2011-09-10target-xtensa: implement memory protection optionsMax Filippov5-13/+782
2011-09-10target-xtensa: add gdb supportMax Filippov3-0/+400
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov3-2/+19
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov2-0/+9
2011-09-10target-xtensa: implement accurate window checkMax Filippov1-0/+110
2011-09-10target-xtensa: implement interrupt optionMax Filippov5-12/+335
2011-09-10target-xtensa: implement SIMCALLMax Filippov2-1/+9
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov3-4/+73
2011-09-10target-xtensa: implement extended L32RMax Filippov3-4/+40
2011-09-10target-xtensa: implement loop optionMax Filippov4-9/+93
2011-09-10target-xtensa: implement windowed registersMax Filippov5-9/+345
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