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target-xtensa
Age
Commit message (
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)
Author
Files
Lines
2011-10-15
target-xtensa: implement MAC16 option
Max Filippov
2
-1
/
+137
2011-10-15
target-xtensa: fix guest hang on masked CCOMPARE interrupt
Max Filippov
2
-15
/
+4
2011-10-01
softmmu_header: pass CPUState to tlb_fill
Blue Swirl
1
-2
/
+3
2011-09-10
target-xtensa: add dc232b core and board
Max Filippov
2
-0
/
+429
2011-09-10
target-xtensa: implement boolean option
Max Filippov
2
-24
/
+86
2011-09-10
target-xtensa: implement memory protection options
Max Filippov
5
-13
/
+782
2011-09-10
target-xtensa: add gdb support
Max Filippov
3
-0
/
+400
2011-09-10
target-xtensa: implement relocatable vectors
Max Filippov
3
-2
/
+19
2011-09-10
target-xtensa: implement CPENABLE and PRID SRs
Max Filippov
2
-0
/
+9
2011-09-10
target-xtensa: implement accurate window check
Max Filippov
1
-0
/
+110
2011-09-10
target-xtensa: implement interrupt option
Max Filippov
5
-12
/
+335
2011-09-10
target-xtensa: implement SIMCALL
Max Filippov
2
-1
/
+9
2011-09-10
target-xtensa: implement unaligned exception option
Max Filippov
3
-4
/
+73
2011-09-10
target-xtensa: implement extended L32R
Max Filippov
3
-4
/
+40
2011-09-10
target-xtensa: implement loop option
Max Filippov
4
-9
/
+93
2011-09-10
target-xtensa: implement windowed registers
Max Filippov
5
-9
/
+345
2011-09-10
target-xtensa: implement RST2 group (32 bit mul/div/rem)
Max Filippov
1
-1
/
+76
2011-09-10
target-xtensa: implement exceptions
Max Filippov
5
-6
/
+236
2011-09-10
target-xtensa: add PS register and access control
Max Filippov
3
-6
/
+77
2011-09-10
target-xtensa: implement CACHE group
Max Filippov
1
-1
/
+94
2011-09-10
target-xtensa: implement SYNC group
Max Filippov
1
-1
/
+30
2011-09-10
target-xtensa: mark reserved and TBD opcodes
Max Filippov
1
-1
/
+109
2011-09-10
target-xtensa: implement LSAI group
Max Filippov
2
-0
/
+90
2011-09-10
target-xtensa: implement shifts (ST1 and RST1 groups)
Max Filippov
4
-0
/
+262
2011-09-10
target-xtensa: implement RST3 group
Max Filippov
1
-0
/
+161
2011-09-10
target-xtensa: add special and user registers
Max Filippov
2
-2
/
+54
2011-09-10
target-xtensa: implement JX/RET0/CALLX
Max Filippov
1
-0
/
+43
2011-09-10
target-xtensa: implement conditional jumps
Max Filippov
1
-0
/
+164
2011-09-10
target-xtensa: implement RT0 group
Max Filippov
1
-0
/
+19
2011-09-10
target-xtensa: implement narrow instructions
Max Filippov
1
-0
/
+54
2011-09-10
target-xtensa: implement disas_xtensa_insn
Max Filippov
5
-2
/
+556
2011-09-10
target-xtensa: add target stubs
Max Filippov
5
-0
/
+326