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AgeCommit message (Expand)AuthorFilesLines
2013-11-08target-xtensa: add missing DEBUG section to dc233c configMax Filippov1-0/+1
2013-10-15target-xtensa: add in_asm loggingMax Filippov1-0/+8
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-2/+0
2013-09-02target: Include softmmu_exec.h where forgottenRichard Henderson1-0/+1
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh1-1/+1
2013-08-05Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into stagingAnthony Liguori3-23/+53
2013-07-29target-xtensa: check register window inlineMax Filippov1-8/+25
2013-07-29target-xtensa: don't generate dead code to access invalid SRsMax Filippov1-13/+18
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov3-2/+8
2013-07-29target-xtensa: add fallthrough markersMax Filippov1-0/+2
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber1-0/+2
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber4-2/+14
2013-07-27gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber1-6/+8
2013-07-27target-xtensa: Move cpu_gdb_{read,write}_register()Andreas Färber1-0/+100
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber2-0/+11
2013-07-26target-xtensa: Introduce XtensaCPU subclassesAndreas Färber3-12/+47
2013-07-23exec: Change cpu_memory_rw_debug() argument to CPUStateAndreas Färber1-5/+5
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber4-5/+10
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+4
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber1-0/+8
2013-07-09target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber1-4/+5
2013-07-09target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber1-2/+3
2013-07-09cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber1-1/+1
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber1-3/+0
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber4-3/+10
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber4-2/+7
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-1/+4
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber1-0/+1
2013-02-23target-xtensa: Use add2/sub2 for macRichard Henderson1-16/+13
2013-02-23target-xtensa: Use mul*2 for mul*hiRichard Henderson1-14/+6
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber1-0/+2
2013-02-16target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber3-13/+9
2013-02-16target-xtensa: Introduce QOM realizefn for XtensaCPUAndreas Färber3-1/+18
2013-02-01target-xtensa: Mark as unmigratableAndreas Färber3-39/+9
2012-12-22target-xtensa: fix search_pc for the last TB opcodeMax Filippov1-1/+5
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini7-7/+7
2012-12-19qom: move include files to include/qom/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini8-19/+19
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-16exec: refactor cpu_restore_stateBlue Swirl1-12/+2
2012-12-15target-xtensa: fix ITLB/DTLB page protection flagsMax Filippov1-1/+2
2012-12-08target-xtensa: use movcond where possibleMax Filippov1-50/+42
2012-12-08target-xtensa: implement MISC SRMax Filippov3-0/+6
2012-12-08target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov1-19/+30
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov3-105/+130
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov5-1/+25
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