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AgeCommit message (Expand)AuthorFilesLines
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber4-2/+7
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-1/+4
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber1-0/+1
2013-02-23target-xtensa: Use add2/sub2 for macRichard Henderson1-16/+13
2013-02-23target-xtensa: Use mul*2 for mul*hiRichard Henderson1-14/+6
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber1-0/+2
2013-02-16target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber3-13/+9
2013-02-16target-xtensa: Introduce QOM realizefn for XtensaCPUAndreas Färber3-1/+18
2013-02-01target-xtensa: Mark as unmigratableAndreas Färber3-39/+9
2012-12-22target-xtensa: fix search_pc for the last TB opcodeMax Filippov1-1/+5
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini7-7/+7
2012-12-19qom: move include files to include/qom/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini8-19/+19
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-16exec: refactor cpu_restore_stateBlue Swirl1-12/+2
2012-12-15target-xtensa: fix ITLB/DTLB page protection flagsMax Filippov1-1/+2
2012-12-08target-xtensa: use movcond where possibleMax Filippov1-50/+42
2012-12-08target-xtensa: implement MISC SRMax Filippov3-0/+6
2012-12-08target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov1-19/+30
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov3-105/+130
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov5-1/+25
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov7-14/+131
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-2/+2
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-10target-xtensa: avoid using cpu_single_envBlue Swirl1-5/+5
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-1/+3
2012-10-28target-xtensa: rename helper flagsAurelien Jarno1-8/+8
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity2-4/+4
2012-10-06target-xtensa: de-optimize EXTUIAurelien Jarno1-20/+2
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov2-0/+43
2012-09-22target-xtensa: implement FP1 groupMax Filippov3-1/+135
2012-09-22target-xtensa: implement FP0 conversionsMax Filippov3-0/+89
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov3-1/+104
2012-09-22target-xtensa: implement LSCX and LSCI groupsMax Filippov1-4/+54
2012-09-22target-xtensa: add FP registersMax Filippov4-7/+63
2012-09-22target-xtensa: handle boolean option in overlaysMax Filippov1-0/+1
2012-09-21target-xtensa: don't emit extra tcg_gen_goto_tbMax Filippov1-1/+3
2012-09-21target-xtensa: fix extui shift amountMax Filippov1-3/+21
2012-09-08target-xtensa: fix missing errno codes for mingw32Max Filippov1-0/+6
2012-09-05target-xtensa: convert host errno values to guestMax Filippov1-8/+98
2012-09-01target-xtensa: return ENOSYS for unimplemented simcallsMax Filippov1-0/+2
2012-08-09Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemuBlue Swirl1-7/+1
2012-08-09target-xtensa: make default CPU depend on target endiannessMax Filippov1-0/+6
2012-07-28target-xtensa: fix big-endian BBS/BBC implementationMax Filippov1-2/+14
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