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2012-09-05target-xtensa: convert host errno values to guestMax Filippov1-8/+98
Guest errno values are taken from the newlib. Convert only those errno values that can be returned from used system calls. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-01target-xtensa: return ENOSYS for unimplemented simcallsMax Filippov1-0/+2
This prevents guest from proceeding with uninitialised garbage returned from unimplemented simcalls. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-08-09Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemuBlue Swirl1-7/+1
* 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemu: target-i386: move tcg initialization into x86_cpu_initfn() cleanup cpu_set_debug_excp_handler target-xtensa: drop usage of prev_debug_excp_handler target-i386: drop usage of prev_debug_excp_handler
2012-08-09target-xtensa: make default CPU depend on target endiannessMax Filippov1-0/+6
This makes usable default for -cpu option both for qemu-system-xtensa and qemu-system-xtensaeb fixing the following error: $ qemu-system-xtensaeb -M sim Unable to find CPU definition Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Tested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-28target-xtensa: fix big-endian BBS/BBC implementationMax Filippov1-2/+14
Quote from ISA, 2.1: For most Xtensa instructions, bit numbering is irrelevant; only the BBC and BBS instructions assign bit numbers to values on which the processor operates. The BBC/BBS instructions use big-endian bit ordering (0 is the most-significant bit) on a big-endian processor configuration. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-25target-xtensa: drop usage of prev_debug_excp_handlerIgor Mammedov1-7/+1
Chains of exception handlers are currently unused feature. Dropping it to be consistent with target-i386 but it may simplify qom-ifying CPU in future like for target-i386. Signed-off-by: Igor Mammedov <imammedo@redhat.com>
2012-06-10target-xtensa: switch to AREG0-free modeMax Filippov4-154/+151
Add env parameter to every helper function that needs it, update 'configure' script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10target-xtensa: add attributes to helper functionsMax Filippov1-8/+8
Mark exception generating functions 'noreturn' and pure constant functions as such. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10target-xtensa: remove unnecessary include of dyngen-exec.hPeter Portante1-1/+0
Signed-off-by: Peter Portante <peter.portante@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-09target-xtensa: fix CCOUNT for conditional branchesMax Filippov1-0/+2
Taken conditional branches fail to update CCOUNT register because accumulated ccount_delta is reset during translation of non-taken branch. To fix it only update CCOUNT once per conditional branch instruction translation. This fixes guest linux freeze on LTP waitpid06 test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-09target-xtensa: control page table lookup explicitlyMax Filippov1-5/+5
Hardware pagetable walking may not be nested. Stop guessing and pass explicit flag to the get_physical_addr_mmu function that controls page table lookup. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-09target-xtensa: update autorefill TLB entries conditionallyMax Filippov3-27/+35
This is to avoid interference of internal QEMU helpers (cpu_get_phys_page_debug, tb_invalidate_virtual_addr) with guest-visible TLB state. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-09target-xtensa: extract TLB entry setting methodMax Filippov2-4/+14
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-09target-xtensa: update EXCVADDR in case of page table lookupMax Filippov1-0/+1
According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, even if the miss is handled entirely by processor hardware. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-09target-xtensa: flush TLB page for new MMU mappingMax Filippov1-0/+1
Both old and new mappings need flushing because their VPN may be different in MMU case. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini1-1/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini1-0/+3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini2-0/+228
Also drop duplicate occurrence of device-hotplug.o. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-04Kill off cpu_state_reset()Andreas Färber1-5/+0
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04target-xtensa: Let cpu_xtensa_init() return XtensaCPUAndreas Färber3-6/+16
Make the include paths for cpu-qom.h consistent to allow using XtensaCPU in cpu.h. Turn cpu_init macro into a static inline function returning CPUXtensaState for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-21target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov1-1/+1
Translation of LOOP instructions used to call LEND SR write handler to update LEND and invalidate relevant TBs. Now that LEND SR write handler ends TB, LOOPNEZ and LOOPGTZ generate wrong code (same as for simple LOOP). Fix it by calling wsr_lend helper directly. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-15target-xtensa: add license to core-fsf.cMax Filippov1-0/+27
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-15target-xtensa: add license to core-dc232b.cMax Filippov1-0/+27
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-15target-xtensa: add dc233c coreMax Filippov3-0/+674
This is Diamond 233L Standard Core Rev.C (LE), implemented through linux/gdb overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov2-11/+20
Instruction breakpoint/zero overhead loop handling code is built into TBs pointed to by IBREAKA/LEND SRs. When these or related SRs get changed TBs at virtual addresses corresponding to their old and their new values must be invalidated. Virtual address range is passed to the tb_invalidate_phys_page_range, which is incorrect in system emulation mode. To fix it use guest TLB/MMU to translate virtual address to physical address. However the guest may not have virtual-to-physical mapping at the moment of IBREAKA/LEND change, thus this fix is not 100% accurate. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-5/+4
Use uintptr_t instead of void * or unsigned long in several op related functions, env->mem_io_pc and GETPC() macro. Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14target-xtensa: Start QOM'ifying CPU initAndreas Färber2-1/+9
Move XtensaConfig-independent code from cpu_xtensa_init() into a QOM initfn, as a start. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber3-14/+14
Move code from cpu_state_reset() into QOM xtensa_cpu_reset(). To avoid moving reset_mmu() and dependencies, make it non-static. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber4-1/+153
Embed CPUXtensaState as first member of XtensaCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova3-4/+4
Provides a file naming scheme consistent with other targets. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber4-68/+68
Scripted conversion: sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc] sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber1-1/+1
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl3-3/+0
* 'upstream' of git://qemu.weilnetz.de/qemu: Move definition of HOST_LONG_BITS to qemu-common.h target-xtensa: Clean includes target-unicore32: Clean includes target-sh4: Clean includes target-s390x: Clean includes target-ppc: Clean includes target-mips: Clean includes target-microblaze: Clean includes target-m68k: Clean includes target-lm32: Clean includes target-i386: Clean includes target-cris: Clean includes target-arm: Clean includes target-alpha: Clean includes Remove macro HOST_LONG_SIZE
2012-02-28target-xtensa: Clean includesStefan Weil3-3/+0
Remove some include statements which are not needed. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-20target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov3-0/+7
Fill debug configuration from overlay definitions in the DEBUG_SECTION. Add DEBUG_SECTION to DC232B and FSF cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov5-0/+147
Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debug watchpoints. This implementation is not fully compliant to ISA: when a breakpoint is set to an unmapped/inaccessible memory address it generates TLB/memory protection exception instead of debug exception. See ISA, 4.7.7.3, 4.7.7.6 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov2-1/+54
ICOUNT SR gets incremented on every instruction completion provided that CINTLEVEL at the beginning of the instruction execution is lower than ICOUNTLEVEL. When ICOUNT would increment to 0 a debug exception is raised if CINTLEVEL is lower than DEBUGLEVEL. See ISA, 4.7.7.5 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov5-3/+119
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and BREAK.N instructions and IBREAK breakpoints. IBREAK breakpoint address is considered constant for TB lifetime. On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov2-0/+21
DEBUGCAUSE SR holds information about the most recent debug exception. See ISA, 4.7.7 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov1-1/+2
According to ISA, 3.5.4, third opcode byte should not be fetched for 2-byte instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov2-0/+68
Command dumps valid ITLB and DTLB entries. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov1-2/+16
TLB_TEMPLATE macro specifies TLB geometry in the core configuration. Make TLB_TEMPLATE available for region protection core variants, defining 1 way ITLB and DTLB with 8 entries each. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-26target-xtensa: fix MMUv3 initializationMax Filippov2-2/+2
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively; - ITLB/DTLB way 6 attr field is set to 3 on reset. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov1-1/+6
This includes opcodes from disabled features and those marked reserved in the ISA. Also end TB on opcodes that definitely generate an exception: illegal instructions, syscall and privileged instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02target-xtensa: handle cache options in the overlay toolMax Filippov1-0/+6
Cache options must be enabled for the cores that have cache to avoid illegal instruction exceptions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov1-1/+1
According to ISA, table 5-156, bits 32:NAREG/4 of the WINDOWSTART SR must be zero. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-10-16target-xtensa: add fsf coreMax Filippov2-0/+383
This is FSF big endian core implemented through linux overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: add dc232b coreMax Filippov3-0/+712
This is Diamond 232L Standard Core Rev.B (LE), implemented through linux/gdb overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov3-13/+554
Introduce overlay_tool.h that defines core configuration blocks from data available in the linux architecture variant overlay. Overlay data is automatically generated in the core configuration process by Tensilica tools and can be directly converted to qemu xtensa core description by overlay_tool.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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