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AgeCommit message (Expand)AuthorFilesLines
2011-10-16target-xtensa: add fsf coreMax Filippov2-0/+383
2011-10-16target-xtensa: add dc232b coreMax Filippov3-0/+712
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov3-13/+554
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov1-0/+3
2011-10-16target-xtensa: remove hand-written xtensa cores implementationsMax Filippov3-860/+2
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov2-8/+12
2011-10-15target-xtensa: implement MAC16 optionMax Filippov2-1/+137
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov2-15/+4
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl1-2/+3
2011-09-10target-xtensa: add dc232b core and boardMax Filippov2-0/+429
2011-09-10target-xtensa: implement boolean optionMax Filippov2-24/+86
2011-09-10target-xtensa: implement memory protection optionsMax Filippov5-13/+782
2011-09-10target-xtensa: add gdb supportMax Filippov3-0/+400
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov3-2/+19
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov2-0/+9
2011-09-10target-xtensa: implement accurate window checkMax Filippov1-0/+110
2011-09-10target-xtensa: implement interrupt optionMax Filippov5-12/+335
2011-09-10target-xtensa: implement SIMCALLMax Filippov2-1/+9
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov3-4/+73
2011-09-10target-xtensa: implement extended L32RMax Filippov3-4/+40
2011-09-10target-xtensa: implement loop optionMax Filippov4-9/+93
2011-09-10target-xtensa: implement windowed registersMax Filippov5-9/+345
2011-09-10target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov1-1/+76
2011-09-10target-xtensa: implement exceptionsMax Filippov5-6/+236
2011-09-10target-xtensa: add PS register and access controlMax Filippov3-6/+77
2011-09-10target-xtensa: implement CACHE groupMax Filippov1-1/+94
2011-09-10target-xtensa: implement SYNC groupMax Filippov1-1/+30
2011-09-10target-xtensa: mark reserved and TBD opcodesMax Filippov1-1/+109
2011-09-10target-xtensa: implement LSAI groupMax Filippov2-0/+90
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov4-0/+262
2011-09-10target-xtensa: implement RST3 groupMax Filippov1-0/+161
2011-09-10target-xtensa: add special and user registersMax Filippov2-2/+54
2011-09-10target-xtensa: implement JX/RET0/CALLXMax Filippov1-0/+43
2011-09-10target-xtensa: implement conditional jumpsMax Filippov1-0/+164
2011-09-10target-xtensa: implement RT0 groupMax Filippov1-0/+19
2011-09-10target-xtensa: implement narrow instructionsMax Filippov1-0/+54
2011-09-10target-xtensa: implement disas_xtensa_insnMax Filippov5-2/+556
2011-09-10target-xtensa: add target stubsMax Filippov5-0/+326
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