Age | Commit message (Expand) | Author | Files | Lines |
2014-06-05 | softmmu: introduce cpu_ldst.h | Paolo Bonzini | 1 | -0/+1 |
2014-05-28 | tcg: Invert the inclusion of helper.h | Richard Henderson | 1 | -3/+2 |
2014-05-26 | target-xtensa: fix cross-page jumps/calls at the end of TB | Max Filippov | 1 | -2/+2 |
2014-03-13 | cpu: Move breakpoints field from CPU_COMMON to CPUState | Andreas Färber | 1 | -2/+3 |
2014-02-24 | target-xtensa: provide HW confg ID registers | Max Filippov | 1 | -2/+7 |
2014-02-24 | target-xtensa: add basic checks to icache opcodes | Max Filippov | 1 | -0/+27 |
2014-02-24 | target-xtensa: add basic checks to dcache opcodes | Max Filippov | 1 | -0/+38 |
2014-02-24 | target-xtensa: add RRRI4 opcode format fields | Max Filippov | 1 | -0/+9 |
2013-10-15 | target-xtensa: add in_asm logging | Max Filippov | 1 | -0/+8 |
2013-10-10 | tcg: Move helper registration into tcg_context_init | Richard Henderson | 1 | -2/+0 |
2013-09-02 | tcg: Change tcg_gen_exit_tb argument to uintptr_t | Richard Henderson | 1 | -1/+1 |
2013-07-29 | target-xtensa: check register window inline | Max Filippov | 1 | -8/+25 |
2013-07-29 | target-xtensa: don't generate dead code to access invalid SRs | Max Filippov | 1 | -13/+18 |
2013-07-29 | target-xtensa: avoid double-stopping at breakpoints | Max Filippov | 1 | -2/+1 |
2013-07-23 | cpu: Move singlestep_enabled field from CPU_COMMON to CPUState | Andreas Färber | 1 | -3/+4 |
2013-07-09 | target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU | Andreas Färber | 1 | -4/+5 |
2013-07-09 | target-xtensa: gen_intermediate_code_internal() should be inlined | Andreas Färber | 1 | -2/+3 |
2013-06-28 | cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks | Andreas Färber | 1 | -2/+4 |
2013-03-03 | gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end | Peter Maydell | 1 | -2/+2 |
2013-02-23 | target-xtensa: Use add2/sub2 for mac | Richard Henderson | 1 | -16/+13 |
2013-02-23 | target-xtensa: Use mul*2 for mul*hi | Richard Henderson | 1 | -14/+6 |
2012-12-22 | target-xtensa: fix search_pc for the last TB opcode | Max Filippov | 1 | -1/+5 |
2012-12-19 | softmmu: move include files to include/sysemu/ | Paolo Bonzini | 1 | -1/+1 |
2012-12-19 | misc: move include files to include/qemu/ | Paolo Bonzini | 1 | -1/+1 |
2012-12-19 | exec: move include files to include/exec/ | Paolo Bonzini | 1 | -2/+2 |
2012-12-19 | build: kill libdis, move disassemblers to disas/ | Paolo Bonzini | 1 | -1/+1 |
2012-12-08 | target-xtensa: use movcond where possible | Max Filippov | 1 | -50/+42 |
2012-12-08 | target-xtensa: implement MISC SR | Max Filippov | 1 | -0/+4 |
2012-12-08 | target-xtensa: better control rsr/wsr/xsr access to SRs | Max Filippov | 1 | -19/+30 |
2012-12-08 | target-xtensa: restrict available SRs by enabled options | Max Filippov | 1 | -104/+126 |
2012-12-08 | target-xtensa: implement CACHEATTR SR | Max Filippov | 1 | -0/+1 |
2012-12-08 | target-xtensa: implement ATOMCTL SR | Max Filippov | 1 | -0/+13 |
2012-12-08 | TCG: Use gen_opc_instr_start from context instead of global variable. | Evgeny Voevodin | 1 | -2/+2 |
2012-12-08 | TCG: Use gen_opc_icount from context instead of global variable. | Evgeny Voevodin | 1 | -1/+1 |
2012-12-08 | TCG: Use gen_opc_pc from context instead of global variable. | Evgeny Voevodin | 1 | -2/+2 |
2012-11-17 | TCG: Use gen_opc_buf from context instead of global variable. | Evgeny Voevodin | 1 | -2/+2 |
2012-11-17 | TCG: Use gen_opc_ptr from context instead of global variable. | Evgeny Voevodin | 1 | -3/+3 |
2012-11-10 | target-xtensa: avoid using cpu_single_env | Blue Swirl | 1 | -5/+5 |
2012-10-06 | target-xtensa: de-optimize EXTUI | Aurelien Jarno | 1 | -20/+2 |
2012-09-27 | Emit debug_insn for CPU_LOG_TB_OP_OPT as well. | Richard Henderson | 1 | -1/+1 |
2012-09-22 | target-xtensa: implement coprocessor context option | Max Filippov | 1 | -0/+38 |
2012-09-22 | target-xtensa: implement FP1 group | Max Filippov | 1 | -1/+80 |
2012-09-22 | target-xtensa: implement FP0 conversions | Max Filippov | 1 | -0/+48 |
2012-09-22 | target-xtensa: implement FP0 arithmetic | Max Filippov | 1 | -1/+60 |
2012-09-22 | target-xtensa: implement LSCX and LSCI groups | Max Filippov | 1 | -4/+54 |
2012-09-22 | target-xtensa: add FP registers | Max Filippov | 1 | -7/+45 |
2012-09-21 | target-xtensa: don't emit extra tcg_gen_goto_tb | Max Filippov | 1 | -1/+3 |
2012-09-21 | target-xtensa: fix extui shift amount | Max Filippov | 1 | -3/+21 |
2012-07-28 | target-xtensa: fix big-endian BBS/BBC implementation | Max Filippov | 1 | -2/+14 |
2012-06-10 | target-xtensa: switch to AREG0-free mode | Max Filippov | 1 | -30/+34 |