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path: root/target-xtensa/translate.c
AgeCommit message (Expand)AuthorFilesLines
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber1-11/+11
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov1-0/+30
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov1-1/+48
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov1-3/+65
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov1-0/+6
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov1-1/+2
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov1-1/+6
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov1-1/+1
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov1-7/+7
2011-10-15target-xtensa: implement MAC16 optionMax Filippov1-1/+134
2011-09-10target-xtensa: implement boolean optionMax Filippov1-24/+85
2011-09-10target-xtensa: implement memory protection optionsMax Filippov1-5/+86
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov1-0/+1
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov1-0/+7
2011-09-10target-xtensa: implement accurate window checkMax Filippov1-0/+110
2011-09-10target-xtensa: implement interrupt optionMax Filippov1-10/+143
2011-09-10target-xtensa: implement SIMCALLMax Filippov1-1/+8
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov1-3/+44
2011-09-10target-xtensa: implement extended L32RMax Filippov1-4/+33
2011-09-10target-xtensa: implement loop optionMax Filippov1-9/+68
2011-09-10target-xtensa: implement windowed registersMax Filippov1-9/+136
2011-09-10target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov1-1/+76
2011-09-10target-xtensa: implement exceptionsMax Filippov1-5/+102
2011-09-10target-xtensa: add PS register and access controlMax Filippov1-5/+24
2011-09-10target-xtensa: implement CACHE groupMax Filippov1-1/+94
2011-09-10target-xtensa: implement SYNC groupMax Filippov1-1/+30
2011-09-10target-xtensa: mark reserved and TBD opcodesMax Filippov1-1/+109
2011-09-10target-xtensa: implement LSAI groupMax Filippov1-0/+89
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov1-0/+242
2011-09-10target-xtensa: implement RST3 groupMax Filippov1-0/+161
2011-09-10target-xtensa: add special and user registersMax Filippov1-2/+47
2011-09-10target-xtensa: implement JX/RET0/CALLXMax Filippov1-0/+43
2011-09-10target-xtensa: implement conditional jumpsMax Filippov1-0/+164
2011-09-10target-xtensa: implement RT0 groupMax Filippov1-0/+19
2011-09-10target-xtensa: implement narrow instructionsMax Filippov1-0/+54
2011-09-10target-xtensa: implement disas_xtensa_insnMax Filippov1-0/+452
2011-09-10target-xtensa: add target stubsMax Filippov1-0/+68
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