Age | Commit message (Expand) | Author | Files | Lines |
2012-07-28 | target-xtensa: fix big-endian BBS/BBC implementation | Max Filippov | 1 | -2/+14 |
2012-06-10 | target-xtensa: switch to AREG0-free mode | Max Filippov | 1 | -30/+34 |
2012-06-09 | target-xtensa: fix CCOUNT for conditional branches | Max Filippov | 1 | -0/+2 |
2012-04-21 | target-xtensa: fix LOOPNEZ/LOOPGTZ translation | Max Filippov | 1 | -1/+1 |
2012-04-14 | target-xtensa: fix tb invalidation for IBREAK and LOOP | Max Filippov | 1 | -0/+2 |
2012-04-14 | target-xtensa: Move helpers.h to helper.h | Lluís Vilanova | 1 | -3/+3 |
2012-03-14 | target-xtensa: Don't overuse CPUState | Andreas Färber | 1 | -11/+11 |
2012-02-20 | target-xtensa: add DBREAK data breakpoints | Max Filippov | 1 | -0/+30 |
2012-02-18 | target-xtensa: add ICOUNT SR and debug exception | Max Filippov | 1 | -1/+48 |
2012-02-18 | target-xtensa: implement instruction breakpoints | Max Filippov | 1 | -3/+65 |
2012-02-18 | target-xtensa: add DEBUGCAUSE SR and configuration | Max Filippov | 1 | -0/+6 |
2012-02-18 | target-xtensa: fetch 3rd opcode byte only when needed | Max Filippov | 1 | -1/+2 |
2011-11-02 | target-xtensa: raise an exception for invalid and reserved opcodes | Max Filippov | 1 | -1/+6 |
2011-11-02 | target-xtensa: mask out undefined bits of WINDOWSTART SR | Max Filippov | 1 | -1/+1 |
2011-10-16 | target-xtensa: increase xtensa options accuracy | Max Filippov | 1 | -7/+7 |
2011-10-15 | target-xtensa: implement MAC16 option | Max Filippov | 1 | -1/+134 |
2011-09-10 | target-xtensa: implement boolean option | Max Filippov | 1 | -24/+85 |
2011-09-10 | target-xtensa: implement memory protection options | Max Filippov | 1 | -5/+86 |
2011-09-10 | target-xtensa: implement relocatable vectors | Max Filippov | 1 | -0/+1 |
2011-09-10 | target-xtensa: implement CPENABLE and PRID SRs | Max Filippov | 1 | -0/+7 |
2011-09-10 | target-xtensa: implement accurate window check | Max Filippov | 1 | -0/+110 |
2011-09-10 | target-xtensa: implement interrupt option | Max Filippov | 1 | -10/+143 |
2011-09-10 | target-xtensa: implement SIMCALL | Max Filippov | 1 | -1/+8 |
2011-09-10 | target-xtensa: implement unaligned exception option | Max Filippov | 1 | -3/+44 |
2011-09-10 | target-xtensa: implement extended L32R | Max Filippov | 1 | -4/+33 |
2011-09-10 | target-xtensa: implement loop option | Max Filippov | 1 | -9/+68 |
2011-09-10 | target-xtensa: implement windowed registers | Max Filippov | 1 | -9/+136 |
2011-09-10 | target-xtensa: implement RST2 group (32 bit mul/div/rem) | Max Filippov | 1 | -1/+76 |
2011-09-10 | target-xtensa: implement exceptions | Max Filippov | 1 | -5/+102 |
2011-09-10 | target-xtensa: add PS register and access control | Max Filippov | 1 | -5/+24 |
2011-09-10 | target-xtensa: implement CACHE group | Max Filippov | 1 | -1/+94 |
2011-09-10 | target-xtensa: implement SYNC group | Max Filippov | 1 | -1/+30 |
2011-09-10 | target-xtensa: mark reserved and TBD opcodes | Max Filippov | 1 | -1/+109 |
2011-09-10 | target-xtensa: implement LSAI group | Max Filippov | 1 | -0/+89 |
2011-09-10 | target-xtensa: implement shifts (ST1 and RST1 groups) | Max Filippov | 1 | -0/+242 |
2011-09-10 | target-xtensa: implement RST3 group | Max Filippov | 1 | -0/+161 |
2011-09-10 | target-xtensa: add special and user registers | Max Filippov | 1 | -2/+47 |
2011-09-10 | target-xtensa: implement JX/RET0/CALLX | Max Filippov | 1 | -0/+43 |
2011-09-10 | target-xtensa: implement conditional jumps | Max Filippov | 1 | -0/+164 |
2011-09-10 | target-xtensa: implement RT0 group | Max Filippov | 1 | -0/+19 |
2011-09-10 | target-xtensa: implement narrow instructions | Max Filippov | 1 | -0/+54 |
2011-09-10 | target-xtensa: implement disas_xtensa_insn | Max Filippov | 1 | -0/+452 |
2011-09-10 | target-xtensa: add target stubs | Max Filippov | 1 | -0/+68 |