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path: root/target-xtensa/overlay_tool.h
AgeCommit message (Expand)AuthorFilesLines
2014-11-03target-xtensa: fix build for cores w/o windowed registersMax Filippov1-12/+19
2014-11-03target-xtensa: add definition for XTHAL_INTTYPE_PROFILINGMax Filippov1-0/+1
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov1-1/+8
2014-02-24target-xtensa: refactor standard core configurationMax Filippov1-0/+10
2012-12-08target-xtensa: implement MISC SRMax Filippov1-0/+1
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov1-1/+3
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov1-0/+1
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov1-0/+6
2012-09-22target-xtensa: handle boolean option in overlaysMax Filippov1-0/+1
2012-02-20target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov1-0/+5
2012-02-18target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov1-2/+16
2011-11-26target-xtensa: fix MMUv3 initializationMax Filippov1-1/+1
2011-11-02target-xtensa: handle cache options in the overlay toolMax Filippov1-0/+6
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov1-0/+534
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