| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2014-02-24 | target-xtensa: provide HW confg ID registers | Max Filippov | 1 | -1/+8 |
| 2014-02-24 | target-xtensa: refactor standard core configuration | Max Filippov | 1 | -0/+10 |
| 2012-12-08 | target-xtensa: implement MISC SR | Max Filippov | 1 | -0/+1 |
| 2012-12-08 | target-xtensa: restrict available SRs by enabled options | Max Filippov | 1 | -1/+3 |
| 2012-12-08 | target-xtensa: implement CACHEATTR SR | Max Filippov | 1 | -0/+1 |
| 2012-12-08 | target-xtensa: implement ATOMCTL SR | Max Filippov | 1 | -0/+6 |
| 2012-09-22 | target-xtensa: handle boolean option in overlays | Max Filippov | 1 | -0/+1 |
| 2012-02-20 | target-xtensa: add DEBUG_SECTION to overlay tool | Max Filippov | 1 | -0/+5 |
| 2012-02-18 | target-xtensa: define TLB_TEMPLATE for MMU-less cores | Max Filippov | 1 | -2/+16 |
| 2011-11-26 | target-xtensa: fix MMUv3 initialization | Max Filippov | 1 | -1/+1 |
| 2011-11-02 | target-xtensa: handle cache options in the overlay tool | Max Filippov | 1 | -0/+6 |
| 2011-10-16 | target-xtensa: extract core configuration from overlay | Max Filippov | 1 | -0/+534 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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