Age | Commit message (Expand) | Author | Files | Lines |
2014-03-13 | cpu: Move watchpoint fields from CPU_COMMON to CPUState | Andreas Färber | 1 | -1/+1 |
2014-03-13 | cpu: Turn cpu_has_work() into a CPUClass hook | Andreas Färber | 1 | -7/+0 |
2014-03-13 | target-xtensa: Clean up ENV_GET_CPU() usage | Andreas Färber | 1 | -1/+3 |
2014-02-24 | target-xtensa: provide HW confg ID registers | Max Filippov | 1 | -0/+4 |
2013-07-29 | target-xtensa: avoid double-stopping at breakpoints | Max Filippov | 1 | -0/+4 |
2013-07-23 | cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb() | Andreas Färber | 1 | -5/+0 |
2013-03-12 | cpu: Replace do_interrupt() by CPUClass::do_interrupt method | Andreas Färber | 1 | -1/+0 |
2013-02-16 | target-xtensa: Move TCG initialization to XtensaCPU initfn | Andreas Färber | 1 | -0/+1 |
2012-12-19 | exec: move include files to include/exec/ | Paolo Bonzini | 1 | -3/+3 |
2012-12-08 | target-xtensa: implement MISC SR | Max Filippov | 1 | -0/+1 |
2012-12-08 | target-xtensa: restrict available SRs by enabled options | Max Filippov | 1 | -0/+1 |
2012-12-08 | target-xtensa: implement CACHEATTR SR | Max Filippov | 1 | -0/+2 |
2012-12-08 | target-xtensa: implement ATOMCTL SR | Max Filippov | 1 | -0/+10 |
2012-10-31 | cpus: Pass CPUState to [qemu_]cpu_has_work() | Andreas Färber | 1 | -1/+3 |
2012-09-22 | target-xtensa: implement coprocessor context option | Max Filippov | 1 | -0/+5 |
2012-09-22 | target-xtensa: add FP registers | Max Filippov | 1 | -0/+3 |
2012-08-09 | target-xtensa: make default CPU depend on target endianness | Max Filippov | 1 | -0/+6 |
2012-06-09 | target-xtensa: update autorefill TLB entries conditionally | Max Filippov | 1 | -1/+1 |
2012-06-09 | target-xtensa: extract TLB entry setting method | Max Filippov | 1 | -0/+3 |
2012-06-04 | target-xtensa: Let cpu_xtensa_init() return XtensaCPU | Andreas Färber | 1 | -3/+13 |
2012-04-14 | target-xtensa: QOM'ify CPU reset | Andreas Färber | 1 | -0/+1 |
2012-04-14 | target-xtensa: QOM'ify CPU | Andreas Färber | 1 | -0/+1 |
2012-03-14 | Rename CPUState -> CPUArchState | Andreas Färber | 1 | -1/+1 |
2012-03-14 | target-xtensa: Don't overuse CPUState | Andreas Färber | 1 | -22/+22 |
2012-02-20 | target-xtensa: add DBREAK data breakpoints | Max Filippov | 1 | -0/+12 |
2012-02-18 | target-xtensa: add ICOUNT SR and debug exception | Max Filippov | 1 | -0/+6 |
2012-02-18 | target-xtensa: implement instruction breakpoints | Max Filippov | 1 | -0/+9 |
2012-02-18 | target-xtensa: add DEBUGCAUSE SR and configuration | Max Filippov | 1 | -0/+15 |
2012-02-18 | target-xtensa: implement info tlb monitor command | Max Filippov | 1 | -0/+1 |
2011-10-16 | target-xtensa: extract core configuration from overlay | Max Filippov | 1 | -0/+6 |
2011-10-16 | target-xtensa: implement external interrupt mapping | Max Filippov | 1 | -0/+3 |
2011-10-16 | target-xtensa: increase xtensa options accuracy | Max Filippov | 1 | -1/+5 |
2011-10-15 | target-xtensa: implement MAC16 option | Max Filippov | 1 | -0/+3 |
2011-10-15 | target-xtensa: fix guest hang on masked CCOMPARE interrupt | Max Filippov | 1 | -0/+1 |
2011-09-10 | target-xtensa: implement boolean option | Max Filippov | 1 | -0/+1 |
2011-09-10 | target-xtensa: implement memory protection options | Max Filippov | 1 | -1/+55 |
2011-09-10 | target-xtensa: add gdb support | Max Filippov | 1 | -0/+14 |
2011-09-10 | target-xtensa: implement relocatable vectors | Max Filippov | 1 | -0/+2 |
2011-09-10 | target-xtensa: implement CPENABLE and PRID SRs | Max Filippov | 1 | -0/+2 |
2011-09-10 | target-xtensa: implement interrupt option | Max Filippov | 1 | -1/+44 |
2011-09-10 | target-xtensa: implement extended L32R | Max Filippov | 1 | -0/+6 |
2011-09-10 | target-xtensa: implement loop option | Max Filippov | 1 | -0/+3 |
2011-09-10 | target-xtensa: implement windowed registers | Max Filippov | 1 | -0/+8 |
2011-09-10 | target-xtensa: implement exceptions | Max Filippov | 1 | -0/+67 |
2011-09-10 | target-xtensa: add PS register and access control | Max Filippov | 1 | -1/+52 |
2011-09-10 | target-xtensa: implement LSAI group | Max Filippov | 1 | -0/+1 |
2011-09-10 | target-xtensa: implement shifts (ST1 and RST1 groups) | Max Filippov | 1 | -0/+4 |
2011-09-10 | target-xtensa: add special and user registers | Max Filippov | 1 | -0/+7 |
2011-09-10 | target-xtensa: implement disas_xtensa_insn | Max Filippov | 1 | -0/+67 |
2011-09-10 | target-xtensa: add target stubs | Max Filippov | 1 | -0/+95 |