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path: root/target-xtensa/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2014-09-12cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell1-1/+1
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini1-0/+1
2014-03-13cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber1-1/+1
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber1-7/+0
2014-03-13target-xtensa: Clean up ENV_GET_CPU() usageAndreas Färber1-1/+3
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov1-0/+4
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov1-0/+4
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber1-1/+0
2013-02-16target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber1-0/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-3/+3
2012-12-08target-xtensa: implement MISC SRMax Filippov1-0/+1
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov1-0/+1
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov1-0/+2
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov1-0/+10
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-1/+3
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov1-0/+5
2012-09-22target-xtensa: add FP registersMax Filippov1-0/+3
2012-08-09target-xtensa: make default CPU depend on target endiannessMax Filippov1-0/+6
2012-06-09target-xtensa: update autorefill TLB entries conditionallyMax Filippov1-1/+1
2012-06-09target-xtensa: extract TLB entry setting methodMax Filippov1-0/+3
2012-06-04target-xtensa: Let cpu_xtensa_init() return XtensaCPUAndreas Färber1-3/+13
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber1-0/+1
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber1-0/+1
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber1-22/+22
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov1-0/+12
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov1-0/+6
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov1-0/+9
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov1-0/+15
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov1-0/+1
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov1-0/+6
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov1-0/+3
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov1-1/+5
2011-10-15target-xtensa: implement MAC16 optionMax Filippov1-0/+3
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov1-0/+1
2011-09-10target-xtensa: implement boolean optionMax Filippov1-0/+1
2011-09-10target-xtensa: implement memory protection optionsMax Filippov1-1/+55
2011-09-10target-xtensa: add gdb supportMax Filippov1-0/+14
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov1-0/+2
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov1-0/+2
2011-09-10target-xtensa: implement interrupt optionMax Filippov1-1/+44
2011-09-10target-xtensa: implement extended L32RMax Filippov1-0/+6
2011-09-10target-xtensa: implement loop optionMax Filippov1-0/+3
2011-09-10target-xtensa: implement windowed registersMax Filippov1-0/+8
2011-09-10target-xtensa: implement exceptionsMax Filippov1-0/+67
2011-09-10target-xtensa: add PS register and access controlMax Filippov1-1/+52
2011-09-10target-xtensa: implement LSAI groupMax Filippov1-0/+1
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov1-0/+4
2011-09-10target-xtensa: add special and user registersMax Filippov1-0/+7
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