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2014-10-20target-tricore: Add instructions of BO opcode formatBastian Koppelmann4-0/+704
2014-10-20target-tricore: Add instructions of BIT opcode formatBastian Koppelmann1-0/+312
2014-10-20target-tricore: Add instructions of B opcode formatBastian Koppelmann1-0/+27
2014-10-20target-tricore: Add instructions of ABS, ABSB opcode formatBastian Koppelmann3-0/+352
2014-10-20target-tricore: Cleanup and BugfixesBastian Koppelmann2-27/+22
2014-09-25target-tricore: Remove the dummy interrupt boilerplateRichard Henderson4-8/+0
2014-09-01target-tricore: Add instructions of SR opcode formatBastian Koppelmann3-0/+164
2014-09-01target-tricore: Add instructions of SLR, SSRO and SRO opcode formatBastian Koppelmann1-0/+121
2014-09-01target-tricore: Add instructions of SC opcode formatBastian Koppelmann3-0/+108
2014-09-01target-tricore: Add instructions of SBR opcode formatBastian Koppelmann1-1/+65
2014-09-01target-tricore: Add instructions of SBC and SBRN opcode formatBastian Koppelmann1-0/+36
2014-09-01target-tricore: Add instructions of SB opcode formatBastian Koppelmann3-0/+276
2014-09-01target-tricore: Add instructions of SRRS and SLRO opcode formatBastian Koppelmann1-0/+59
2014-09-01target-tricore: Add instructions of SSR opcode formatBastian Koppelmann1-0/+50
2014-09-01target-tricore: Add instructions of SRR opcode formatBastian Koppelmann3-0/+211
2014-09-01target-tricore: Add instructions of SRC opcode formatBastian Koppelmann2-0/+267
2014-09-01target-tricore: Add masks and opcodes for decodingBastian Koppelmann2-0/+1407
2014-09-01target-tricore: Add initialization for translation and activate targetBastian Koppelmann1-0/+165
2014-09-01target-tricore: Add softmmu supportBastian Koppelmann2-2/+85
2014-09-01target-tricore: Add target stubs and qom-cpuBastian Koppelmann9-0/+916
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