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target-tricore
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2015-05-22
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
Bastian Koppelmann
4
-0
/
+74
2015-05-22
target-tricore: add FRET instructions of the v1.6 ISA
Bastian Koppelmann
2
-0
/
+21
2015-05-22
target-tricore: add FCALL instructions of the v1.6 ISA
Bastian Koppelmann
2
-0
/
+29
2015-05-22
target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
Bastian Koppelmann
2
-0
/
+11
2015-05-22
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
Bastian Koppelmann
4
-0
/
+19
2015-05-22
target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
Bastian Koppelmann
2
-0
/
+44
2015-05-22
target-tricore: add CMPSWP instructions of the v1.6.1 ISA
Bastian Koppelmann
2
-0
/
+40
2015-05-22
target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
Bastian Koppelmann
1
-2
/
+9
2015-05-22
target-tricore: introduce ISA v1.6.1 feature
Bastian Koppelmann
2
-3
/
+8
2015-05-22
target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3
Bastian Koppelmann
1
-0
/
+8
2015-05-11
target-tricore: fix rfe not restoring the PC
Bastian Koppelmann
1
-0
/
+1
2015-05-11
target-tricore: fix rslcx restoring the upper context instead of the lower
Bastian Koppelmann
1
-1
/
+1
2015-05-11
target-tricore: fix BO_OFF10_SEXT calculating the wrong offset
Bastian Koppelmann
1
-1
/
+1
2015-05-11
target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...
Bastian Koppelmann
1
-2
/
+2
2015-05-11
target-tricore: Fix LOOP using wrong register for compare
Bastian Koppelmann
1
-1
/
+1
2015-04-30
tcg: Delete unused cpu_pc_from_tb()
Peter Crosthwaite
1
-5
/
+0
2015-04-04
target-tricore: Fix check which was always false
Stefan Weil
1
-1
/
+1
2015-03-30
target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
Bastian Koppelmann
1
-4
/
+4
2015-03-24
target-tricore: properly fix dvinit_b/h_13
Bastian Koppelmann
1
-30
/
+10
2015-03-24
target-tricore: fix RRPW_DEXTR using wrong reg
Bastian Koppelmann
1
-2
/
+2
2015-03-24
target-tricore: fix DVINIT_HU/BU calculating overflow before result
Bastian Koppelmann
1
-12
/
+18
2015-03-24
target-tricore: Fix two helper functions (clang warnings)
Stefan Weil
1
-6
/
+6
2015-03-19
Fix typos in comments
Viswesh
1
-11
/
+11
2015-03-16
target-tricore: Add instructions of SYS opcode format
Bastian Koppelmann
4
-0
/
+175
2015-03-16
target-tricore: Add instructions of RRRW opcode format
Bastian Koppelmann
1
-0
/
+63
2015-03-16
target-tricore: Add instructions of RRRR opcode format
Bastian Koppelmann
1
-0
/
+56
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...
Bastian Koppelmann
4
-2
/
+415
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...
Bastian Koppelmann
4
-2
/
+600
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...
Bastian Koppelmann
4
-24
/
+493
2015-03-13
tcg: Change translator-side labels to a pointer
Richard Henderson
1
-4
/
+2
2015-03-10
cpu: Make cpu_init() return QOM CPUState object
Eduardo Habkost
1
-9
/
+1
2015-03-03
target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...
Bastian Koppelmann
3
-0
/
+418
2015-03-03
target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...
Bastian Koppelmann
4
-4
/
+588
2015-03-03
target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi...
Bastian Koppelmann
3
-0
/
+534
2015-03-03
target-tricore: Add instructions of RRR2 opcode format
Bastian Koppelmann
2
-15
/
+136
2015-03-03
target-tricore: fix msub32_suov return wrong results
Bastian Koppelmann
1
-6
/
+21
2015-03-03
target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper
Bastian Koppelmann
1
-2
/
+2
2015-02-12
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
Richard Henderson
1
-3
/
+1
2015-02-12
tcg: Move emit of INDEX_op_end into gen_tb_end
Richard Henderson
1
-1
/
+0
2015-01-27
target-tricore: Add instructions of RRR opcode format
Bastian Koppelmann
4
-1
/
+319
2015-01-27
target-tricore: Add instructions of RRPW opcode format
Bastian Koppelmann
1
-0
/
+70
2015-01-27
target-tricore: Add instructions of RR2 opcode format
Bastian Koppelmann
1
-0
/
+37
2015-01-27
target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...
Bastian Koppelmann
1
-0
/
+182
2015-01-26
target-tricore: split up suov32 into suov32_pos and suov32_neg
Bastian Koppelmann
1
-15
/
+26
2015-01-26
target-tricore: Fix bugs found by coverity
Bastian Koppelmann
2
-1
/
+3
2015-01-26
target-tricore: calculate av bits before saturation
Bastian Koppelmann
1
-12
/
+16
2015-01-26
target-tricore: Several translator and cpu model fixes
Bastian Koppelmann
3
-4
/
+5
2015-01-26
target-tricore: Add missing ULL suffix on 64 bit constant
Peter Maydell
1
-1
/
+1
2015-01-15
target-tricore: Fix new typos
Stefan Weil
3
-4
/
+4
2015-01-09
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
1
-1
/
+1
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