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target-tricore
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Author
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Lines
2015-01-27
target-tricore: Add instructions of RRR opcode format
Bastian Koppelmann
4
-1
/
+319
2015-01-27
target-tricore: Add instructions of RRPW opcode format
Bastian Koppelmann
1
-0
/
+70
2015-01-27
target-tricore: Add instructions of RR2 opcode format
Bastian Koppelmann
1
-0
/
+37
2015-01-27
target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...
Bastian Koppelmann
1
-0
/
+182
2015-01-26
target-tricore: split up suov32 into suov32_pos and suov32_neg
Bastian Koppelmann
1
-15
/
+26
2015-01-26
target-tricore: Fix bugs found by coverity
Bastian Koppelmann
2
-1
/
+3
2015-01-26
target-tricore: calculate av bits before saturation
Bastian Koppelmann
1
-12
/
+16
2015-01-26
target-tricore: Several translator and cpu model fixes
Bastian Koppelmann
3
-4
/
+5
2015-01-26
target-tricore: Add missing ULL suffix on 64 bit constant
Peter Maydell
1
-1
/
+1
2015-01-15
target-tricore: Fix new typos
Stefan Weil
3
-4
/
+4
2015-01-09
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
1
-1
/
+1
2015-01-03
gen-icount: check cflags instead of use_icount global
Paolo Bonzini
1
-1
/
+1
2014-12-21
target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs...
Bastian Koppelmann
3
-0
/
+273
2014-12-21
target-tricore: Fix MFCR/MTCR insn and B format offset.
Bastian Koppelmann
2
-2
/
+6
2014-12-21
target-tricore: Add missing 1.6 insn of BOL opcode format
Bastian Koppelmann
2
-1
/
+54
2014-12-21
target-tricore: Add instructions of RR opcode format, that have 0x4b as the f...
Bastian Koppelmann
4
-1
/
+390
2014-12-21
target-tricore: Add instructions of RR opcode format, that have 0x1 as the fi...
Bastian Koppelmann
1
-0
/
+97
2014-12-21
target-tricore: Add instructions of RR opcode format, that have 0xf as the fi...
Bastian Koppelmann
3
-0
/
+250
2014-12-21
target-tricore: Add instructions of RR opcode format, that have 0xb as the fi...
Bastian Koppelmann
4
-2
/
+942
2014-12-21
target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
Bastian Koppelmann
1
-76
/
+58
2014-12-21
target-tricore: Fix mask handling JNZ.T being 7 bit long
Bastian Koppelmann
1
-2
/
+2
2014-12-21
target-tricore: pretty-print register dump and show more status registers
Alex Zuepke
1
-6
/
+15
2014-12-21
target-tricore: add missing 64-bit MOV in RLC format
Alex Zuepke
2
-0
/
+13
2014-12-21
target-tricore: typo in BOL format
Alex Zuepke
2
-3
/
+3
2014-12-21
target-tricore: fix offset masking in BOL format
Alex Zuepke
1
-1
/
+1
2014-12-10
target-tricore: Add instructions of RCR opcode format
Bastian Koppelmann
4
-1
/
+657
2014-12-10
target-tricore: Add instructions of RLC opcode format
Bastian Koppelmann
5
-0
/
+252
2014-12-10
target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format
Bastian Koppelmann
1
-3
/
+129
2014-12-10
target-tricore: Make TRICORE_FEATURES implying others.
Bastian Koppelmann
2
-3
/
+12
2014-12-10
target-tricore: Add instructions of RC opcode format
Bastian Koppelmann
4
-0
/
+799
2014-12-10
target-tricore: Add instructions of BRR opcode format
Bastian Koppelmann
2
-2
/
+89
2014-12-10
target-tricore: Add instructions of BRN opcode format
Bastian Koppelmann
2
-0
/
+27
2014-12-10
target-tricore: Add instructions of BRC opcode format
Bastian Koppelmann
2
-3
/
+56
2014-12-10
target-tricore: Add instructions of BOL opcode format
Bastian Koppelmann
2
-1
/
+51
2014-10-20
target-tricore: Add instructions of BO opcode format
Bastian Koppelmann
4
-0
/
+704
2014-10-20
target-tricore: Add instructions of BIT opcode format
Bastian Koppelmann
1
-0
/
+312
2014-10-20
target-tricore: Add instructions of B opcode format
Bastian Koppelmann
1
-0
/
+27
2014-10-20
target-tricore: Add instructions of ABS, ABSB opcode format
Bastian Koppelmann
3
-0
/
+352
2014-10-20
target-tricore: Cleanup and Bugfixes
Bastian Koppelmann
2
-27
/
+22
2014-09-25
target-tricore: Remove the dummy interrupt boilerplate
Richard Henderson
4
-8
/
+0
2014-09-01
target-tricore: Add instructions of SR opcode format
Bastian Koppelmann
3
-0
/
+164
2014-09-01
target-tricore: Add instructions of SLR, SSRO and SRO opcode format
Bastian Koppelmann
1
-0
/
+121
2014-09-01
target-tricore: Add instructions of SC opcode format
Bastian Koppelmann
3
-0
/
+108
2014-09-01
target-tricore: Add instructions of SBR opcode format
Bastian Koppelmann
1
-1
/
+65
2014-09-01
target-tricore: Add instructions of SBC and SBRN opcode format
Bastian Koppelmann
1
-0
/
+36
2014-09-01
target-tricore: Add instructions of SB opcode format
Bastian Koppelmann
3
-0
/
+276
2014-09-01
target-tricore: Add instructions of SRRS and SLRO opcode format
Bastian Koppelmann
1
-0
/
+59
2014-09-01
target-tricore: Add instructions of SSR opcode format
Bastian Koppelmann
1
-0
/
+50
2014-09-01
target-tricore: Add instructions of SRR opcode format
Bastian Koppelmann
3
-0
/
+211
2014-09-01
target-tricore: Add instructions of SRC opcode format
Bastian Koppelmann
2
-0
/
+267
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