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target-tricore
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2014-09-25
target-tricore: Remove the dummy interrupt boilerplate
Richard Henderson
4
-8
/
+0
2014-09-01
target-tricore: Add instructions of SR opcode format
Bastian Koppelmann
3
-0
/
+164
2014-09-01
target-tricore: Add instructions of SLR, SSRO and SRO opcode format
Bastian Koppelmann
1
-0
/
+121
2014-09-01
target-tricore: Add instructions of SC opcode format
Bastian Koppelmann
3
-0
/
+108
2014-09-01
target-tricore: Add instructions of SBR opcode format
Bastian Koppelmann
1
-1
/
+65
2014-09-01
target-tricore: Add instructions of SBC and SBRN opcode format
Bastian Koppelmann
1
-0
/
+36
2014-09-01
target-tricore: Add instructions of SB opcode format
Bastian Koppelmann
3
-0
/
+276
2014-09-01
target-tricore: Add instructions of SRRS and SLRO opcode format
Bastian Koppelmann
1
-0
/
+59
2014-09-01
target-tricore: Add instructions of SSR opcode format
Bastian Koppelmann
1
-0
/
+50
2014-09-01
target-tricore: Add instructions of SRR opcode format
Bastian Koppelmann
3
-0
/
+211
2014-09-01
target-tricore: Add instructions of SRC opcode format
Bastian Koppelmann
2
-0
/
+267
2014-09-01
target-tricore: Add masks and opcodes for decoding
Bastian Koppelmann
2
-0
/
+1407
2014-09-01
target-tricore: Add initialization for translation and activate target
Bastian Koppelmann
1
-0
/
+165
2014-09-01
target-tricore: Add softmmu support
Bastian Koppelmann
2
-2
/
+85
2014-09-01
target-tricore: Add target stubs and qom-cpu
Bastian Koppelmann
9
-0
/
+916