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2015-06-29target-tricore: fix depositing bits from PCXI into ICRPaolo Bonzini1-2/+2
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-05-30target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann1-1/+1
2015-05-30target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann1-11/+0
2015-05-30target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann1-1/+1
2015-05-22target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann4-0/+74
2015-05-22target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann2-0/+21
2015-05-22target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann2-0/+29
2015-05-22target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann2-0/+11
2015-05-22target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann4-0/+19
2015-05-22target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann2-0/+44
2015-05-22target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann2-0/+40
2015-05-22target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann1-2/+9
2015-05-22target-tricore: introduce ISA v1.6.1 featureBastian Koppelmann2-3/+8
2015-05-22target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3Bastian Koppelmann1-0/+8
2015-05-11target-tricore: fix rfe not restoring the PCBastian Koppelmann1-0/+1
2015-05-11target-tricore: fix rslcx restoring the upper context instead of the lowerBastian Koppelmann1-1/+1
2015-05-11target-tricore: fix BO_OFF10_SEXT calculating the wrong offsetBastian Koppelmann1-1/+1
2015-05-11target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann1-2/+2
2015-05-11target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann1-1/+1
2015-04-30tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite1-5/+0
2015-04-04target-tricore: Fix check which was always falseStefan Weil1-1/+1
2015-03-30target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann1-4/+4
2015-03-24target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann1-30/+10
2015-03-24target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann1-2/+2
2015-03-24target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann1-12/+18
2015-03-24target-tricore: Fix two helper functions (clang warnings)Stefan Weil1-6/+6
2015-03-19Fix typos in commentsViswesh1-11/+11
2015-03-16target-tricore: Add instructions of SYS opcode formatBastian Koppelmann4-0/+175
2015-03-16target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann1-0/+63
2015-03-16target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann1-0/+56
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann4-2/+415
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann4-2/+600
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann4-24/+493
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-4/+2
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost1-9/+1
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...Bastian Koppelmann3-0/+418
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...Bastian Koppelmann4-4/+588
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi...Bastian Koppelmann3-0/+534
2015-03-03target-tricore: Add instructions of RRR2 opcode formatBastian Koppelmann2-15/+136
2015-03-03target-tricore: fix msub32_suov return wrong resultsBastian Koppelmann1-6/+21
2015-03-03target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helperBastian Koppelmann1-2/+2
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-3/+1
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+0
2015-01-27target-tricore: Add instructions of RRR opcode formatBastian Koppelmann4-1/+319
2015-01-27target-tricore: Add instructions of RRPW opcode formatBastian Koppelmann1-0/+70
2015-01-27target-tricore: Add instructions of RR2 opcode formatBastian Koppelmann1-0/+37
2015-01-27target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...Bastian Koppelmann1-0/+182
2015-01-26target-tricore: split up suov32 into suov32_pos and suov32_negBastian Koppelmann1-15/+26
2015-01-26target-tricore: Fix bugs found by coverityBastian Koppelmann2-1/+3
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