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2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-37/+4
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-2/+3
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-0/+3
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson1-1/+0
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-1/+2
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-4/+2
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-15target-tilegx: Handle v1shl, v1shru, v1shrsRichard Henderson4-2/+76
2015-09-15target-tilegx: Handle v1shli, v1shruiRichard Henderson1-0/+14
2015-09-15target-tilegx: Handle v4int_l/hRichard Henderson1-0/+8
2015-09-15target-tilegx: Handle atomic instructionsRichard Henderson2-2/+82
2015-09-15target-tilegx: Handle mtspr, mfsprRichard Henderson1-3/+73
2015-09-15target-tilegx: Handle v1cmpeq, v1cmpneRichard Henderson1-0/+51
2015-09-15target-tilegx: Handle mask instructionsRichard Henderson1-2/+9
2015-09-15target-tilegx: Handle scalar multiply instructionsRichard Henderson1-0/+112
2015-09-15target-tilegx: Handle conditional move instructionsRichard Henderson1-1/+8
2015-09-15target-tilegx: Handle shift instructionsRichard Henderson1-2/+54
2015-09-15target-tilegx: Handle bitfield instructionsRichard Henderson1-0/+74
2015-09-15target-tilegx: Implement system and memory management instructionsRichard Henderson1-23/+54
2015-09-15target-tilegx: Handle comparison instructionsRichard Henderson1-6/+33
2015-09-15target-tilegx: Handle conditional branch instructionsRichard Henderson1-13/+38
2015-09-15target-tilegx: Handle unconditional jump instructionsRichard Henderson1-17/+41
2015-09-15target-tilegx: Handle post-increment load and store instructionsRichard Henderson1-8/+86
2015-09-15target-tilegx: Handle basic load and store instructionsRichard Henderson1-15/+115
2015-09-15target-tilegx: Handle most bit manipulation instructionsRichard Henderson3-1/+79
2015-09-15target-tilegx: Handle arithmetic instructionsRichard Henderson1-6/+90
2015-09-15target-tilegx: Handle simple logical operationsRichard Henderson1-3/+96
2015-09-15target-tilegx: Add TILE-Gx building filesChen Gang1-0/+1
2015-09-15target-tilegx: Generate SEGV properlyRichard Henderson2-1/+6
2015-09-15target-tilegx: Framework for decoding bundlesRichard Henderson1-0/+1145
2015-09-15target-tilegx: Add several helpers for instructions translationChen Gang2-0/+74
2015-09-15target-tilegx: Add cpu basic features for linux-userChen Gang2-0/+345
2015-09-15target-tilegx: Add special register information from Tilera CorporationChen Gang1-0/+216
2015-09-15target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1Richard Henderson1-1/+1
2015-09-15target-tilegx: Modify _SPECIAL_ opcodesRichard Henderson1-2/+2
2015-09-15target-tilegx: Modify opcode_tilegx.h to fit QEMU usageChen Gang1-110/+110
2015-09-15target-tilegx: Add opcode basic implementation from Tilera CorporationChen Gang1-0/+1406
generated by cgit v1.1 at 2024-12-27 08:23:25 +0000