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2015-01-20target-sparc: Don't use {ld, st}*_raw functionsPeter Maydell1-12/+12
Instead of using the _raw family of ld/st accessor functions, use cpu_*_data. All this code is CONFIG_USER_ONLY, so the two are the same semantically, but the _raw functions are really a detail of the implementation which has leaked into a few callsites like this one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1421334118-3287-4-git-send-email-peter.maydell@linaro.org
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell1-2/+0
The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-12-16qemu-log: add log category for MMU infoAntony Pavlov1-4/+3
Running barebox on qemu-system-mips* with '-d unimp' overloads stderr by very very many mips_cpu_handle_mmu_fault() messages: mips_cpu_handle_mmu_fault address=b80003fd ret 0 physical 00000000180003fd prot 3 mips_cpu_handle_mmu_fault address=a0800884 ret 0 physical 0000000000800884 prot 3 mips_cpu_handle_mmu_fault pc a080cd80 ad b80003fd rw 0 mmu_idx 0 So it's very difficult to find LOG_UNIMP message. The mips_cpu_handle_mmu_fault() messages appear on enabling ANY logging! It's not very handy. Adding separate log category for *_cpu_handle_mmu_fault() logging fixes the problem. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1418489298-1184-1-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-sparc: Use cpu_exec_interrupt qom hookRichard Henderson1-0/+21
Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-16-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-17target-sparc64: implement Short Floating-Point Store InstructionsArtyom Tarasenko1-1/+14
Implement Short Floating-Point Store Instructions as described in the chapter 13.5.2 of UltraSPARC-IIi User's Manual. Particularly this instructions are used by NetBSD 4.0.1+ /sparc64 Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini2-4/+2
This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-13/+0
They do not need to be in op_helper.c. Because cputlb.c now includes softmmu_template.h twice for each size, io_readX must be elided the second time through. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2-1/+2
Prepare for moving softmmu_header.h inclusion out of .c files Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05softmmu: make do_unaligned_access a method of CPUPaolo Bonzini3-7/+10
We will reference it from more files in the next patch. To avoid ruining the small steps we're making towards multi-target, make it a method of CPU rather than just a global. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson9-14/+9
Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-26target-sparc: fix 32bit integer division overflowOlivier Danet1-7/+10
The signed integer division -0x8000_0000_0000_0000 / -1 must be handled separately to avoid an overflow on the QEMU host. Negative overflow must be a negative number for correct sign extension in Sparc64 mode. Use <stdint.h> constants. Signed-off-by: Olivier Danet <odanet@caramail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-3/+3
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber3-10/+13
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber1-3/+6
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber2-2/+2
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2-11/+17
This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2-4/+4
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-3/+5
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber3-3/+4
Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber5-22/+26
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber4-10/+18
Note that while such functions may exist both for *-user and softmmu, only *-user uses the CPUState hook, while softmmu reuses the prototype for calling it directly. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13target-sparc: Defer SPARCCPU feature inference to QOM realizeAndreas Färber1-5/+8
Gets it out of cpu_sparc_register() and aligns with target-arm. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13target-sparc: Implement CPUClass::parse_features() for SPARCCPUAndreas Färber1-33/+49
Factor cpu_model parsing out of cpu_sparc_find_by_name() by passing cpu_sparc_find_by_name() the name portion only and calling CPUClass::parse_features() from cpu_sparc_register() afterwards. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13target-sparc: Use error_report() for CPU error reportingAndreas Färber1-8/+9
Replace non-debug fprintf() with error_report(). Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2-9/+10
Default to false. Tidy variable naming and inline cast uses while at it. Tested-by: Jia Liu <proljc@gmail.com> (or32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13target-sparc: Clean up ENV_GET_CPU() usageAndreas Färber2-12/+9
Commits fdfba1a298ae26dd44bcfdb0429314139a0bc55a, 2c17449b3022ca9623c4a7e2a504a4150ac4ad30 and f606604f1c10b60ef294f1b9b229426521a365e3 added usages of ENV_GET_CPU() macro in target-specific code. Use sparc_env_get_cpu() instead and reuse the variables. Cc: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-12target-sparc: Add and use CPU_FEATURE_CASASebastian Huber5-32/+56
The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to generate C11 atomic operations. The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is not defined use a supervisor data load/store for an ASI of 0x80 in helper_ld_asi()/helper_st_asi(). The supervisor data load/store was choosen according to the LEON3 documentation. The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted access, Primary address space. Tested with the following program: #include <assert.h> #include <stdatomic.h> void test(void) { atomic_int a; int e; _Bool b; atomic_store(&a, 1); e = 1; b = atomic_compare_exchange_strong(&a, &e, 2); assert(b); assert(atomic_load(&a) == 2); atomic_store(&a, 3); e = 4; b = atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) == 3); } Tested also on a NGMP board with a LEON4 processor. Reviewed-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-02-11exec: Make stb_phys input an AddressSpaceEdgar E. Iglesias1-3/+3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stw_*_phys input an AddressSpaceEdgar E. Iglesias1-3/+3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stl_phys_notdirty input an AddressSpaceEdgar E. Iglesias1-1/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias1-3/+3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stq_*_phys input an AddressSpaceEdgar E. Iglesias1-7/+8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make lduw_*_phys input an AddressSpaceEdgar E. Iglesias1-3/+3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias1-10/+15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias2-12/+16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-01-15SPARC: Fix LEON3 power down instructionSebastian Huber1-0/+1
Synchronize the program counter before the power down helper call otherwise interrupts will return to the wrong context. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2013-12-02misc: Replace 'struct QEMUTimer' by 'QEMUTimer'Stefan Weil1-1/+1
Most code already used QEMUTimer without the redundant 'struct' keyword. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-10-11Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori2-14/+9
# By Richard Henderson # Via Richard Henderson * rth/tcg-pull: exec: Add both big- and little-endian memory helpers tcg: Add qemu_ld_st_i32/64 tcg: Add TCGMemOp configure: Remove CONFIG_QEMU_LDST_OPTIMIZATION tcg: Add tcg-be-ldst.h tcg: Add tcg-be-null.h exec: Delete is_tcg_gen_code and GETRA_EXT tcg-aarch64: Update to helper_ret_*_mmu routines tcg: Merge tcg_register_helper into tcg_context_init tcg: Add tcg-runtime.c helpers to all_helpers tcg: Put target helper data into an array. tcg: Remove stray semi-colons from target-*/helper.h tcg: Move helper registration into tcg_context_init target-m68k: Rename helpers.h to helper.h tcg: Use a GHashTable for tcg_find_helper tcg: Delete tcg_helper_get_name declaration tcg-hppa: Remove tcg backend Message-id: 1381440525-6666-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-9/+9
During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-5/+0
No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-07cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber1-1/+0
Since this is only read in cpu_copy() and linux-user has a global cpu_model, drop the field from generic code. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber1-0/+2
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code. This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed". The reason for the failure is that CPUClass::kvm_fd is not yet initialized in the following call graph: ->x86_cpu_realizefn ->x86_cpu_apic_realize ->qdev_init ->device_set_realized ->device_reset (hotplugged == 1) ->apic_reset_common ->vapic_base_update ->kvm_apic_vapic_base_update This causes attempted KVM vCPU ioctls to fail. By contrast, in the non-hotplug case the APIC is reset much later, when the vCPU is already initialized. As a quick and safe solution, move the qemu_init_vcpu() call back into the targets' realize functions. Reported-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Acked-by: Igor Mammedov <imammedo@redhat.com> (for i386) Tested-by: Jia Liu <proljc@gmail.com> (for openrisc) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber4-2/+15
Completes migration of target-specific code to new target-*/gdbstub.c. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber1-27/+27
This avoids polluting the global namespace with a non-prefixed macro and makes it obvious in the call sites that we return. Semi-automatic conversion using, e.g., sed -i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target-*/gdbstub.c followed by manual tweaking for sparc's GET_REGA() and Coding Style. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-26target-sparc: Move cpu_gdb_{read,write}_register()Andreas Färber1-0/+200
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber1-0/+6
CPUState::gdb_num_regs replaces num_g_regs. CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS. Allows building gdb_register_coprocessor() for xtensa, too. As a side effect this should fix coprocessor register numbering for SMP. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Introduce CPUClass::memory_rw_debug() for target_memory_rw_debug()Andreas Färber3-6/+10
Make inline target_memory_rw_debug() always available and change its argument to CPUState. Let it check if CPUClass::memory_rw_debug provides a specialized callback and fall back to cpu_memory_rw_debug() otherwise. The only overriding implementation is for 32-bit sparc. This prepares for changing GDBState::g_cpu to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
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