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target-sparc
Age
Commit message (
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Author
Files
Lines
2008-11-18
Refactor and enhance break/watchpoint API (Jan Kiszka)
aliguori
1
-3
/
+4
2008-11-18
Refactor translation block CPU state handling (Jan Kiszka)
aliguori
1
-0
/
+16
2008-11-18
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
aliguori
1
-5
/
+7
2008-11-17
TCG variable type checking.
pbrook
3
-632
/
+627
2008-11-09
Use TCG not op
blueswir1
1
-14
/
+12
2008-11-09
Use andc, orc, nor and nand
blueswir1
1
-52
/
+36
2008-11-01
Fix TCGv size mismatches
blueswir1
1
-19
/
+21
2008-10-07
Add static (spotted by sparse)
blueswir1
1
-1
/
+1
2008-10-07
Fix error in fexpand (spotted by sparse)
blueswir1
1
-4
/
+4
2008-10-06
Show size for unassigned accesses (Robert Reif)
blueswir1
2
-14
/
+15
2008-10-03
Rearrange tick functions
blueswir1
3
-31
/
+31
2008-10-03
Fix missing prototype warnings by moving declarations
blueswir1
2
-11
/
+9
2008-10-02
Fix MXCC printf warning (based on patch by Robert Reif)
blueswir1
1
-3
/
+3
2008-09-27
Add mmu tlb demap support (Igor Kovalenko)
blueswir1
1
-1
/
+35
2008-09-26
Add a generic Niagara machine
blueswir1
2
-2
/
+2
2008-09-26
Implement some UA2007 block ASIs
blueswir1
1
-0
/
+6
2008-09-26
Implement UA2005 hypervisor traps
blueswir1
3
-18
/
+23
2008-09-26
Move also DEBUG_PCALL (see r5085)
blueswir1
2
-1
/
+1
2008-09-22
Add software and timer interrupt support
blueswir1
4
-5
/
+49
2008-09-22
Fix arguments used in cas/casx, thanks to Igor Kovalenko for spotting
blueswir1
1
-5
/
+5
2008-09-21
Use the new concat_tl_i64 op for std and stda
blueswir1
1
-18
/
+6
2008-09-21
Use the new concat_i32_i64 op for std and stda
blueswir1
3
-22
/
+20
2008-09-20
Move signal handler prototype back to cpu.h
blueswir1
2
-1
/
+1
2008-09-14
Fix array subscript above array bounds error
blueswir1
1
-1
/
+1
2008-09-13
Fix mulscc with high bits set in either src1 or src2
blueswir1
1
-2
/
+3
2008-09-11
Write zeros to high bits of y, based on patch by Vince Weaver
blueswir1
1
-2
/
+4
2008-09-10
Convert rest of ops using float32 to TCG, remove FT0 and FT1
blueswir1
5
-64
/
+39
2008-09-10
Partially convert float128 conversion ops to TCG
blueswir1
3
-20
/
+19
2008-09-10
Convert basic 64 bit VIS ops to TCG
blueswir1
4
-102
/
+65
2008-09-10
Convert basic 32 bit VIS ops to TCG
blueswir1
3
-164
/
+48
2008-09-10
Convert basic float32 ops to TCG
blueswir1
3
-190
/
+329
2008-09-09
Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG
blueswir1
5
-31
/
+43
2008-09-06
Fix a typo in fpsub32
blueswir1
1
-1
/
+1
2008-09-06
Convert most env fields to TCG registers
blueswir1
1
-95
/
+91
2008-09-06
Silence gcc warning about constant overflow
blueswir1
2
-3
/
+11
2008-09-03
Implement no-fault loads
blueswir1
1
-8
/
+36
2008-09-02
Fix sign extension problems with smul and umul (Vince Weaver)
blueswir1
1
-4
/
+4
2008-09-01
Fix y register loads and stores
blueswir1
1
-18
/
+16
2008-08-30
Remove memcpy32() prototype leftover from r5109
blueswir1
1
-1
/
+0
2008-08-29
Fix FCC handling for Sparc64 target, initial patch by Vince Weaver
blueswir1
2
-30
/
+28
2008-08-29
Fix Sparc64 boot on i386 host:
blueswir1
5
-273
/
+280
2008-08-25
Fix udiv and sdiv on Sparc64 (Vince Weaver)
blueswir1
1
-2
/
+2
2008-08-21
Fix wrwim masking (Luis Pureza)
blueswir1
1
-0
/
+3
2008-08-21
Use initial CPU definition structure for some CPU fields instead of copying
blueswir1
4
-87
/
+83
2008-08-17
Correct 32bit carry flag for add instruction (Igor Kovalenko)
blueswir1
1
-5
/
+8
2008-08-06
Fix faligndata (Vince Weaver)
blueswir1
1
-1
/
+4
2008-08-06
Fix I/D MMU tag reads
blueswir1
1
-54
/
+4
2008-08-06
Fix Sparc64 shifts
blueswir1
1
-5
/
+3
2008-08-06
Fix offset handling for ASI loads and stores (Vince Weaver)
blueswir1
1
-3
/
+1
2008-08-01
Handle wrapped registers correctly when saving
blueswir1
1
-1
/
+11
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