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AgeCommit message (Expand)AuthorFilesLines
2008-11-01Fix TCGv size mismatchesblueswir11-19/+21
2008-10-07Add static (spotted by sparse)blueswir11-1/+1
2008-10-07Fix error in fexpand (spotted by sparse)blueswir11-4/+4
2008-10-06Show size for unassigned accesses (Robert Reif)blueswir12-14/+15
2008-10-03Rearrange tick functionsblueswir13-31/+31
2008-10-03Fix missing prototype warnings by moving declarationsblueswir12-11/+9
2008-10-02Fix MXCC printf warning (based on patch by Robert Reif)blueswir11-3/+3
2008-09-27Add mmu tlb demap support (Igor Kovalenko)blueswir11-1/+35
2008-09-26Add a generic Niagara machineblueswir12-2/+2
2008-09-26Implement some UA2007 block ASIsblueswir11-0/+6
2008-09-26Implement UA2005 hypervisor trapsblueswir13-18/+23
2008-09-26Move also DEBUG_PCALL (see r5085)blueswir12-1/+1
2008-09-22Add software and timer interrupt supportblueswir14-5/+49
2008-09-22Fix arguments used in cas/casx, thanks to Igor Kovalenko for spottingblueswir11-5/+5
2008-09-21Use the new concat_tl_i64 op for std and stdablueswir11-18/+6
2008-09-21Use the new concat_i32_i64 op for std and stdablueswir13-22/+20
2008-09-20Move signal handler prototype back to cpu.hblueswir12-1/+1
2008-09-14Fix array subscript above array bounds errorblueswir11-1/+1
2008-09-13Fix mulscc with high bits set in either src1 or src2blueswir11-2/+3
2008-09-11Write zeros to high bits of y, based on patch by Vince Weaverblueswir11-2/+4
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir15-64/+39
2008-09-10Partially convert float128 conversion ops to TCGblueswir13-20/+19
2008-09-10Convert basic 64 bit VIS ops to TCGblueswir14-102/+65
2008-09-10Convert basic 32 bit VIS ops to TCGblueswir13-164/+48
2008-09-10Convert basic float32 ops to TCGblueswir13-190/+329
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir15-31/+43
2008-09-06Fix a typo in fpsub32blueswir11-1/+1
2008-09-06Convert most env fields to TCG registersblueswir11-95/+91
2008-09-06Silence gcc warning about constant overflowblueswir12-3/+11
2008-09-03Implement no-fault loadsblueswir11-8/+36
2008-09-02Fix sign extension problems with smul and umul (Vince Weaver)blueswir11-4/+4
2008-09-01Fix y register loads and storesblueswir11-18/+16
2008-08-30Remove memcpy32() prototype leftover from r5109blueswir11-1/+0
2008-08-29Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir12-30/+28
2008-08-29Fix Sparc64 boot on i386 host:blueswir15-273/+280
2008-08-25Fix udiv and sdiv on Sparc64 (Vince Weaver)blueswir11-2/+2
2008-08-21Fix wrwim masking (Luis Pureza)blueswir11-0/+3
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir14-87/+83
2008-08-17Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir11-5/+8
2008-08-06Fix faligndata (Vince Weaver)blueswir11-1/+4
2008-08-06Fix I/D MMU tag readsblueswir11-54/+4
2008-08-06Fix Sparc64 shiftsblueswir11-5/+3
2008-08-06Fix offset handling for ASI loads and stores (Vince Weaver)blueswir11-3/+1
2008-08-01Handle wrapped registers correctly when savingblueswir11-1/+11
2008-07-29Fix cmp/subcc/addcc op bugs reported by Vince Weaverblueswir11-4/+4
2008-07-25Make MAXTL dynamic, bounds check tl when indexingblueswir14-51/+56
2008-07-24Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir12-4/+110
2008-07-22Add T1 and T2 CPUs, add a Sun4v machineblueswir13-1/+26
2008-07-21Use MMU globals for some MMU trapsblueswir12-4/+19
2008-07-21Fix reset vectorblueswir11-1/+1
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