aboutsummaryrefslogtreecommitdiff
path: root/target-sparc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2012-10-07target-sparc: Use DisasCompare in TccRichard Henderson1-9/+11
2012-10-07target-sparc: Introduce DisasCompare and functions to generate itRichard Henderson1-9/+83
2012-10-07target-sparc: Tidy gen_generic_branch interfaceRichard Henderson1-8/+7
2012-10-07target-sparc: Tidy save_npc interfaceRichard Henderson1-4/+4
2012-10-07target-sparc: Tidy gen_mov_pc_npc interfaceRichard Henderson1-6/+6
2012-10-07target-sparc: Tidy save_state interfaceRichard Henderson1-49/+49
2012-10-07target-sparc: Tidy gen_trap_ifnofpu interfaceRichard Henderson1-18/+28
2012-10-07target-sparc: Tidy flush_cond interfaceRichard Henderson1-5/+5
2012-10-07target-sparc: Tidy do_branch interfacesRichard Henderson1-20/+18
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+2
2012-05-12Implement address masking for SPARC v9 CPUsArtyom Tarasenko1-1/+24
2012-03-18Sparc: avoid AREG0 wrappers for memory access helpersBlue Swirl1-4/+6
2012-03-18Sparc: avoid AREG0 for memory access helpersBlue Swirl1-25/+27
2012-03-14target-sparc: Don't overuse CPUStateAndreas Färber1-40/+40
2011-11-19Improve "ta 0" shutdownFabien Chouteau1-8/+1
2011-10-26target-sparc: Implement FALIGNDATA inline.Richard Henderson1-6/+26
2011-10-26target-sparc: Implement BMASK/BSHUFFLE.Richard Henderson1-4/+10
2011-10-26target-sparc: Implement ALIGNADDR* inline.Richard Henderson1-2/+22
2011-10-26target-sparc: Implement EDGE* instructions.Richard Henderson1-2/+175
2011-10-26target-sparc: Implement fpack{16,32,fix}.Richard Henderson1-1/+29
2011-10-26target-sparc: Implement PDIST.Richard Henderson1-2/+19
2011-10-26target-sparc: Do exceptions management fully inside the helpers.Richard Henderson1-29/+0
2011-10-26target-sparc: Change fpr representation to doubles.Richard Henderson1-79/+71
2011-10-26target-sparc: Undo cpu_fpr rename.Richard Henderson1-28/+28
2011-10-26target-sparc: Extract float128 move to a function.Richard Henderson1-32/+18
2011-10-26target-sparc: Extract common code for floating-point operations.Richard Henderson1-454/+381
2011-10-26target-sparc: Make FPU/VIS helpers const when possible.Richard Henderson1-50/+33
2011-10-26target-sparc: Pass float64 parameters instead of dt0/1 temporaries.Richard Henderson1-229/+220
2011-10-26target-sparc: Add accessors for double-precision fpr access.Richard Henderson1-112/+130
2011-10-26target-sparc: Mark fprs dirty in store accessor.Richard Henderson1-46/+8
2011-10-26target-sparc: Add accessors for single-precision fpr access.Richard Henderson1-195/+337
2011-10-26Sparc: avoid AREG0 for division op helpersBlue Swirl1-4/+8
2011-10-26Sparc: avoid AREG0 for softint op helpers and Leon cache controlBlue Swirl1-3/+3
2011-10-26Sparc: avoid AREG0 for CWP and PSTATE helpersBlue Swirl1-17/+17
2011-10-25target-sparc: Fix order of function parametersStefan Weil1-4/+4
2011-10-23Sparc: avoid AREG0 for lazy condition code helpersBlue Swirl1-9/+9
2011-10-23Sparc: avoid AREG0 for float and VIS opsBlue Swirl1-133/+137
2011-10-23Sparc: avoid AREG0 for raise_exception and helper_debugBlue Swirl1-13/+13
2011-08-06Fix handling of conditional branches in delay slot of a conditional branchArtyom Tarasenko1-9/+21
2011-07-30SPARC64: implement %fprs dirty bitsTsuneo Saito1-0/+116
2011-07-30SPARC64: fix fnor* and fnand*Tsuneo Saito1-6/+8
2011-07-20SPARC64: add missing break on fmovdccTsuneo Saito1-0/+1
2011-07-20SPARC64: fix VIS1 SIMD signed compare instructionsTsuneo Saito1-16/+16
2011-07-14Sparc: fix FPU and AM enable checks for translationBlue Swirl1-7/+2
2011-07-14SPARC64: fp_disabled checks on stfa/stdfa/stqfaTsuneo Saito1-0/+9
2011-07-14SPARC64: Implement stfa/stdfa/stqfa instrcutions properlyTsuneo Saito1-2/+0
2011-07-14SPARC64: fp_disabled checks on ldfa/lddfa/ldqfaTsuneo Saito1-0/+9
2011-07-01fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivxArtyom Tarasenko1-10/+22
2011-06-26Remove exec-all.h include directivesBlue Swirl1-1/+0
2011-05-22Delete unused tb_invalidate_page_rangeBlue Swirl1-1/+1
generated by cgit v1.1 at 2024-12-28 11:19:48 +0000