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path: root/target-sparc/translate.c
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2011-07-20SPARC64: add missing break on fmovdccTsuneo Saito1-0/+1
"break" is missing on V9 fmovdcc (%icc). Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20SPARC64: fix VIS1 SIMD signed compare instructionsTsuneo Saito1-16/+16
The destination registers of SIMD signed compare instructions (fcmp*<16|32>) are not FP registers but general purpose r registers. Comparisons should be freg_rs1 CMP freg_rs2, that were reversed. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14Sparc: fix FPU and AM enable checks for translationBlue Swirl1-7/+2
Translation used incorrectly CPUState fields directly to check for FPU enable state and 32 bit address masking on Sparc64. Fix by using TB flags instead. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14SPARC64: fp_disabled checks on stfa/stdfa/stqfaTsuneo Saito1-0/+9
stfa/stdfa/stqfa instructions should raise fp_disabled exceptions if %pstate.PEF==0 or %fprs.FEF==0. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14SPARC64: Implement stfa/stdfa/stqfa instrcutions properlyTsuneo Saito1-2/+0
This patch implements sparcv9 stfa/stdfa/stqfa instructions with non block-store ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14SPARC64: fp_disabled checks on ldfa/lddfa/ldqfaTsuneo Saito1-0/+9
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions if %pstate.PEF==0 or %fprs.FEF==0. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivxArtyom Tarasenko1-10/+22
udivx and sdvix don't modify condition flags, so they shall not overwrite cpu_cc_* Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Remove exec-all.h include directivesBlue Swirl1-1/+0
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-22Delete unused tb_invalidate_page_rangeBlue Swirl1-1/+1
tb_invalidate_page_range() was intended to be used to invalidate an area of a TB which the guest explicitly flushes from i-cache. However, QEMU detects writes to code areas where TBs have been generated, so his has never been useful. Delete the function, adjust callers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-14sparc64: fix incorrect BPcc target sign extensionBlue Swirl1-1/+1
Fix wrong number of bits used when sign extending the branch offset of BPcc instructions. Reported-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-14sparc64: fix wrpstate and wrtl on delay slotBlue Swirl1-8/+20
Use TCG local to work around TCG register flush due to a branch. Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-04-20Remove unused function parameters from gen_pc_load and rename the functionStefan Weil1-2/+1
Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-10Fix conversions from pointer to tcg_target_longStefan Weil1-1/+1
tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-24SPARC: Add asr17 register supportFabien Chouteau1-0/+11
This register is activated by CPU_FEATURE_ASR17 in the feature field. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-24SPARC: Emulation of Leon3Fabien Chouteau1-2/+11
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more information on http://www.gaisler.com). Leon3 is made of multiple components available in the GrLib VHDL library. Three devices are implemented: uart, timers and IRQ manager. You can find code for these peripherals in the grlib_* files. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-28target-sparc: fix udiv(cc) and sdiv(cc)Aurelien Jarno1-6/+6
Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes on a Debian Etch image. The commit itself is fine, but it triggers a bug due to wrong computation of flags for udiv(cc) and sdiv(cc). This patch only compute cc_src2 for the cc version of udiv/sdiv. It also moves the update of cc_dst and cc_op to the helper, as it is faster doing it here when there is already an helper. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-02sparc64: fix umul and smul insnsIgor V. Kovalenko1-26/+29
- truncate and sign or zero extend operands before multiplication - factor out common code to gen_op_multiply() with parameter to sign/zero extend - call gen_op_multiply from gen_op_umul and gen_op_smul Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-02sparc64: fix ldxfsr insnIgor V. Kovalenko1-1/+5
- rearrange code to break from switch when appropriate - allow deprecated ldfsr insn Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-02sparc64: fix missing address masking v1Igor V. Kovalenko1-0/+4
- address masking for ldqf and stqf insns - address masking for lddf and stdf insns - address masking for translating ASI (Ultrasparc IIi) v0->v1: - move arch-specific code to helpers and drop more ifdefs at call sites using new helper asi_address_mask() - change user emulation to use asi_address_mask() Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22sparc64: fix mmu context at trap levels above zeroIgor V. Kovalenko1-3/+7
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero - cpu_get_tb_cpu_state: store trap level and primary context in flags this allows to restart code translation when address translation is changed - stop translation block after writing to pstate and tl registers - stop translation block after writing to alternate space this can be optimized to stop only if address translation can be changed by write operation (e.g. by comparing with MMU ASI values) Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22sparc64: fix pstate privilege bitsIgor V. Kovalenko1-2/+2
- refactor code to handle hpstate only if available for current cpu - conditionally set hypervisor bit in hpstate register - reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well - disable sparcv8 registers for TARGET_SPARC64 - fix cpu_mmu_index to use sparcv9 bits only Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-20target-sparc: Inline some generation of carry for ADDX/SUBX.Richard Henderson1-74/+198
Computing carry is trivial for some inputs. By avoiding an external function call, we generate near-optimal code for the common cases of add+addx (double-word arithmetic) and cmp+addx (a setcc pattern). Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-09sparc: lazy C flag calculationBlue Swirl1-16/+8
Calculate only the carry flag for ADDX/SUBX instead of full set of flags. Thanks to Igor Kovalenko for spotting a bug with an earlier version. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-26target-sparc: Fix -singlestep.Richard Henderson1-4/+5
Single-stepping was not properly updating npc, resulting in some instructions being executed twice. In addition, we were emitting dead code at the end of the TB. Fix both by teaching gen_goto_tb to avoid goto_tb for single-step and removing the special-case code in gen_intermediate_code_internal. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-18Fix harmless if statements with empty body, spotted by clangBlue Swirl1-1/+2
These clang errors are harmless but worth fixing: CC ppc-softmmu/usb-ohci.o /src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body] ohci->ctrl_head, ohci->ctrl_cur); /src/qemu/hw/usb-ohci.c:1371:57: error: if statement has empty body [-Wempty-body] DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum); CC sparc64-softmmu/translate.o /src/qemu/target-sparc/translate.c:3173:37: error: if statement has empty body [-Wempty-body] ; // XXX Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-17target-sparc: Free instruction temporaries.Richard Henderson1-25/+27
Rather than creating new temporaries for constants, use the ones created in disas_sparc_insn. Remember the temps created there so that they can be freed at the end of the function. Profile data collected by TCG while booting sparc-test kernel: -avg temps/TB 70.61 max=421 +avg temps/TB 62.75 max=66 Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-17Sparc: fix PC/NPC during FPU trapsBlue Swirl1-0/+2
All FPU instructions can trap, so save PC/NPC state before executing them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-11Sparc: fix exceptions in delay slotBlue Swirl1-4/+4
Fix a case where an exception happens with the instruction in the delay slot. Recovery of branch condition in the exception handling code was not converted to TCG. Because the condition was bogus, wrong NPC could be selected from the two candidates. A nice bug report with a test case can be found in: https://bugs.launchpad.net/qemu/+bug/551814 Fix based on patch by Fabrice Bellard. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-08remove TARGET_* defines from translate-all.cPaolo Bonzini1-0/+3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-25target-sparc: fix --enable-debug build for 64 bit hostStefan Weil1-1/+1
b551ec04ca45d1925417dd2ec7c1b7f115c84f1d fixed the compilation for 32 bit hosts, but introduced a new error for 64 bit hosts: tcg_temp_new_ptr needs a matching tcg_temp_free_ptr. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20target-sparc: fix --enable-debug buildJay Foad1-11/+11
Use 32-bit arithmetic for the address offset calculation to fix a build failure on 32-bit hosts. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-08sparc64: use helper_wrpil to check pending irq on writeIgor V. Kovalenko1-4/+1
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-23sparc64-8bit-asiIgor V. Kovalenko1-0/+1
Sparc64 alternate space load/store helpers expect 8 bit ASI value, while wrasi implementation sign-extends ASI operand causing for example 0x80 to appear as 0xFFFFFF80. Resulting value falls out of switch in helpers and causes obscure load/store faults. - correct wrasi by masking lower 8 bits of xor result - use lower 8 bits of ASI register in helpers Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12Fix sys-queue.h conflict for goodBlue Swirl1-2/+2
Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-22Sparc32/64: fix jmpl followed by branchBlue Swirl1-0/+2
Fix a case where 'jmpl' instruction followed by a branch instruction was handled incorrectly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-15Fix desynchronization of condition code state when a memory access trapsBlue Swirl1-0/+11
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-04Sparc64: replace tsptr with helper routineIgor Kovalenko1-16/+35
tl and tsptr of members sparc64 cpu state must be changed simultaneously to keep trap state window in sync with current trap level. Currently translation of store to tl does not change tsptr, which leads to corrupt trap state on corresponding trap level. This patch removes tsptr from sparc64 cpu state and replaces all uses with call to helper routine. Changes v0->v1: - reimplemented helper routine with tcg generator - on cpu reset trap type and pstate are populated with power-on reset values, including tl=maxtl Signed-off-by: igor.v.kovalenko@gmail.com Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-31sparc64 flush pending conditional evaluations before exposing cpu stateIgor Kovalenko1-0/+5
If translation block is interrupted by e.g. mmu exception we need to compute conditional flags for inclusion into saved cpu state. Otherwise after return from trap conditional instructions would use stale psr/xcc data. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-06Use correct type for SPARC cpu_cc_opPaul Brook1-1/+2
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-10Convert mulsccBlue Swirl1-131/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert udiv/sdivBlue Swirl1-19/+6
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert tagged opsBlue Swirl1-129/+8
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert subxBlue Swirl1-31/+6
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert subBlue Swirl1-37/+11
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert logical operations and umul/smulBlue Swirl1-24/+24
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert addxBlue Swirl1-31/+6
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert addBlue Swirl1-21/+6
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Use dynamical computation for condition codesBlue Swirl1-24/+108
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-03Optimize cmp x, 0 caseBlue Swirl1-14/+19
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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